8 Central Processing Unit
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3/23/2004
Ted Borys - CSI 404
Section 8
Page 8-1
Major Components of CPU z
Register set
Central Processing Unit
Holds intermediate data used during instruction execution
z
Arithmetic Logic Unit (ALU)
z
Control unit
Performs microoperations for executing instructions Supervises data transfers among registers Tells ALU which operation to perform
Slides with white background courtesy of Mano text for this class 1
Major Components of CPU
2
R1 ← R2 + R3 z
MUX A selector (SELA)
z
MUX B selector (SELB)
z
ALU operation selector (OPR)
z
Register Set & ALU
Put content of R3 on bus B Perform arithmetic addition A + B
Decoder destination selector (SELD)
3
Put content of R2 on bus A
Transfer content of output bus into R1
4
Register Selection Field Encoding
Control word
Block diagram
© 2004 by Ted Borys. All rights reserved.
5
6
3/23/2004
Ted Borys - CSI 404
ALU Function Table
Page 8-2
ALU Operation Encoding
7
CPU Microoperations Examples
8
Stack z z
Last-in first-out (LIFO) list Stack pointer (SP)
z
Always points to top item in stack Register that holds stack address
Operations
Push – put new item in top of stack Pop – remove item from top of stack
9
64-Word Stack Block Diagram
Stack Initialization
Registers: FULL – one bit EMTY – one bit SP – six bit DR – stack I/O
11
© 2004 by Ted Borys. All rights reserved.
10
z z z
SP cleared to 0 EMTY set to 1 FULL cleared to 0
12
3/23/2004
Ted Borys - CSI 404
Push z z z z
Page 8-3
Pop
SP ← SP + 1 M[SP] ← DR If (SP = 0) then (FULL ← 1) EMTY ← 0
z z z z
DR ← M[SP] SP ← SP – 1 If (SP = 0) then (EMTY ← 1) FULL ← 0
13
Memory Layout Example
14
Arithmetic Expression Notations
In this example, PUSH decrements SP POP increments SP
z z z
A+B +AB AB+
Infix Prefix or Polish Postfix or reverse Polish
15
RPN Processing Algorithm z z
z
z
RPN Example
Scan expression from left to right When you find an operator
z z
Apply it to the two previous operands Replace operator and two operands just used with result
A * B + C * D becomes A B * C D * + Stepwise evaluation
Resume left to right scan, repeat above steps until no more operators Works well with a stack
17
© 2004 by Ted Borys. All rights reserved.
16
AB*CD*+ (A * B) C D * + where (A * B) is a single value (A * B) (C * D) + where (C * D) is a single value ((A * B) + (C * D)) which is a single value
18
Ted Borys - CSI 404
3/23/2004
Another RPN Example z z
Another Infix to RP
8 * 2 + 5 * 3 becomes 8 2 * 5 3 * + Stepwise evaluation
Page 8-4
z z
8 2*5 3*+ 16 5 3 * + 16 15 + 31
z
Infix (A + B) * (C * (D + E) + F) RP AB+DE+C*F+* RPN doesn’t need or use parentheses
19
Stack Operations z z
Infix: RP:
20
Types of CPU Organizations
3*4+5*6 3 4*5 6*+
z z z z
Single accumulator General register Stack Some CPUs combine features from more than one organization type
21
Single Accumulator z
ADD
22
General Register
X
z
AC ← AC + M[X]
ADD
z
ADD
z
z
23
© 2004 by Ted Borys. All rights reserved.
R1, R2
R1 ← R2
ADD
R1, R2
R1 ← R1 + R2
MOV
R1, R2, R3
R1 ← R2 + R3
R1, X
R1 ← R1 + M[X]
24
Ted Borys - CSI 404
3/23/2004
Stack z z
Three Address Instructions
PUSH X ADD
Page 8-5
z z
Zero address Pop two numbers off stack Add them Push result back on stack
X = (A + B) * (C + D) ADD R1, A, B R1 ← M[A] + M[B] ADD R2, C, D R2 ← M[C] + M[D] MUL X, R1, R2 M[X] ← R1 * R2
25
Two Address Instructions z z
26
One Address Instructions
X = (A + B) * (C + D) MOV R1, A ADD R1, B MOV R2, C ADD R2, D MUL R1, R2 MOV X, R1
z z
X = (A + B) * (C + D) LOAD A ADD B STORE T LOAD C ADD D MUL T STORE X
27
Zero Address Instructions z z
RISC Instructions
X = (A + B) * (C + D) PUSH A PUSH B ADD PUSH C PUSH D ADD MUL POP X
z
z
29
© 2004 by Ted Borys. All rights reserved.
28
Only load and store instructions can reference memory All other instructions can only reference registers
30
3/23/2004
Ted Borys - CSI 404
RISC Instructions z z
Page 8-6
Addressing Mode Techniques
X = (A + B) * (C + D) LOAD R1, A LOAD R2, B LOAD R3, C LOAD R4, D ADD R1, R1, R2 ADD R3, R3, R4 MUL R1, R1, R3 STORE X, R1
z
Useful for
Reducing the number of bits in the address field of the instruction Writing programming loops, indexing data, using memory pointers, relocating programs in memory
31
Addressing Modes z
z z z z
More Addressing Modes
Implied – operands specified implicitly
32
z
E.g., “complement accumulator”
Immediate – operand value in address field Register – operand in register specified in register field Register Indirect – register contains indirect address Autoincrement or Autodecrement – like register indirect, except register value is incremented or decremented after it is used
z
z
z
z
Direct Address – effective address is in address part of the instruction Indirect Address – effective address is stored in memory location specified in address part of the instruction Relative Address – program counter added to address part of the instruction Indexed Addressing – value of index register added to address part of the instruction to yield effective address Base Register Addressing – similar to Indexed
33
Addressing Modes Example
34
Numerical Example
Direct Immediate Indirect Relative Indexed Register Register Indirect Autoincrement Autodecrement
35
© 2004 by Ted Borys. All rights reserved.
36
Ted Borys - CSI 404
Section 8
Page 8-1
Major Components of CPU z
Register set
Central Processing Unit
Holds intermediate data used during instruction execution
z
Arithmetic Logic Unit (ALU)
z
Control unit
Performs microoperations for executing instructions Supervises data transfers among registers Tells ALU which operation to perform
Slides with white background courtesy of Mano text for this class 1
Major Components of CPU
2
R1 ← R2 + R3 z
MUX A selector (SELA)
z
MUX B selector (SELB)
z
ALU operation selector (OPR)
z
Register Set & ALU
Put content of R3 on bus B Perform arithmetic addition A + B
Decoder destination selector (SELD)
3
Put content of R2 on bus A
Transfer content of output bus into R1
4
Register Selection Field Encoding
Control word
Block diagram
© 2004 by Ted Borys. All rights reserved.
5
6
3/23/2004
Ted Borys - CSI 404
ALU Function Table
Page 8-2
ALU Operation Encoding
7
CPU Microoperations Examples
8
Stack z z
Last-in first-out (LIFO) list Stack pointer (SP)
z
Always points to top item in stack Register that holds stack address
Operations
Push – put new item in top of stack Pop – remove item from top of stack
9
64-Word Stack Block Diagram
Stack Initialization
Registers: FULL – one bit EMTY – one bit SP – six bit DR – stack I/O
11
© 2004 by Ted Borys. All rights reserved.
10
z z z
SP cleared to 0 EMTY set to 1 FULL cleared to 0
12
3/23/2004
Ted Borys - CSI 404
Push z z z z
Page 8-3
Pop
SP ← SP + 1 M[SP] ← DR If (SP = 0) then (FULL ← 1) EMTY ← 0
z z z z
DR ← M[SP] SP ← SP – 1 If (SP = 0) then (EMTY ← 1) FULL ← 0
13
Memory Layout Example
14
Arithmetic Expression Notations
In this example, PUSH decrements SP POP increments SP
z z z
A+B +AB AB+
Infix Prefix or Polish Postfix or reverse Polish
15
RPN Processing Algorithm z z
z
z
RPN Example
Scan expression from left to right When you find an operator
z z
Apply it to the two previous operands Replace operator and two operands just used with result
A * B + C * D becomes A B * C D * + Stepwise evaluation
Resume left to right scan, repeat above steps until no more operators Works well with a stack
17
© 2004 by Ted Borys. All rights reserved.
16
AB*CD*+ (A * B) C D * + where (A * B) is a single value (A * B) (C * D) + where (C * D) is a single value ((A * B) + (C * D)) which is a single value
18
Ted Borys - CSI 404
3/23/2004
Another RPN Example z z
Another Infix to RP
8 * 2 + 5 * 3 becomes 8 2 * 5 3 * + Stepwise evaluation
Page 8-4
z z
8 2*5 3*+ 16 5 3 * + 16 15 + 31
z
Infix (A + B) * (C * (D + E) + F) RP AB+DE+C*F+* RPN doesn’t need or use parentheses
19
Stack Operations z z
Infix: RP:
20
Types of CPU Organizations
3*4+5*6 3 4*5 6*+
z z z z
Single accumulator General register Stack Some CPUs combine features from more than one organization type
21
Single Accumulator z
ADD
22
General Register
X
z
AC ← AC + M[X]
ADD
z
ADD
z
z
23
© 2004 by Ted Borys. All rights reserved.
R1, R2
R1 ← R2
ADD
R1, R2
R1 ← R1 + R2
MOV
R1, R2, R3
R1 ← R2 + R3
R1, X
R1 ← R1 + M[X]
24
Ted Borys - CSI 404
3/23/2004
Stack z z
Three Address Instructions
PUSH X ADD
Page 8-5
z z
Zero address Pop two numbers off stack Add them Push result back on stack
X = (A + B) * (C + D) ADD R1, A, B R1 ← M[A] + M[B] ADD R2, C, D R2 ← M[C] + M[D] MUL X, R1, R2 M[X] ← R1 * R2
25
Two Address Instructions z z
26
One Address Instructions
X = (A + B) * (C + D) MOV R1, A ADD R1, B MOV R2, C ADD R2, D MUL R1, R2 MOV X, R1
z z
X = (A + B) * (C + D) LOAD A ADD B STORE T LOAD C ADD D MUL T STORE X
27
Zero Address Instructions z z
RISC Instructions
X = (A + B) * (C + D) PUSH A PUSH B ADD PUSH C PUSH D ADD MUL POP X
z
z
29
© 2004 by Ted Borys. All rights reserved.
28
Only load and store instructions can reference memory All other instructions can only reference registers
30
3/23/2004
Ted Borys - CSI 404
RISC Instructions z z
Page 8-6
Addressing Mode Techniques
X = (A + B) * (C + D) LOAD R1, A LOAD R2, B LOAD R3, C LOAD R4, D ADD R1, R1, R2 ADD R3, R3, R4 MUL R1, R1, R3 STORE X, R1
z
Useful for
Reducing the number of bits in the address field of the instruction Writing programming loops, indexing data, using memory pointers, relocating programs in memory
31
Addressing Modes z
z z z z
More Addressing Modes
Implied – operands specified implicitly
32
z
E.g., “complement accumulator”
Immediate – operand value in address field Register – operand in register specified in register field Register Indirect – register contains indirect address Autoincrement or Autodecrement – like register indirect, except register value is incremented or decremented after it is used
z
z
z
z
Direct Address – effective address is in address part of the instruction Indirect Address – effective address is stored in memory location specified in address part of the instruction Relative Address – program counter added to address part of the instruction Indexed Addressing – value of index register added to address part of the instruction to yield effective address Base Register Addressing – similar to Indexed
33
Addressing Modes Example
34
Numerical Example
Direct Immediate Indirect Relative Indexed Register Register Indirect Autoincrement Autodecrement
35
© 2004 by Ted Borys. All rights reserved.
36
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