6803

---------------------------------------------------------------| | | | | Motorola | | | | 666 88888 000 33333 | | 6 8 8 0 0 3 3 | | 6 8 8 0 0 0 3 | | 666666 88888 0 0 0 33333 | | 6 6 8 8 0 0 0 3 | | 6 6 8 8 0 0 3 3 | | 66666 88888 000 33333 | | | | 6803/6803NR Single-Chip MICROCOMPUTER | | Instruction Set Summary | | | | | | | | | | _________ _________ | | _| \__/ |_ | | Vss |_|1 40|_| E --> | | _| |_ | | --> XTAL1 |_|2 39|_| AS | | _| |_ _ | | --> EXTAL2 |_|3 38|_| R/W --> | | ___ _| |_ | | --> NMI |_|4 37|_| D0/A0 <--> | | ___ _| |_ | | --> IRQ1 |_|5 36|_| D1/A1 <--> | | _| |_ | | --> Reset |_|6 35|_| D2/A2 <--> | | _| |_ | | Vcc |_|7 34|_| D3/A3 <--> | | _| |_ | | <--> P20 |_|8 33|_| D4/A4 <--> | | _| |_ | | <--> P21 |_|9 32|_| D5/A5 <--> | | _| |_ | | <--> P22 |_|10 6803 31|_| D6/A6 <--> | | _| |_ | | <--> P23 |_|11 30|_| D7/A7 <--> | | _| |_ | | <--> P24 |_|12 29|_| A8 --> | | _| |_ | | <--> P10 |_|13 28|_| A9 --> | | _| |_ | | <--> P11 |_|14 27|_| A10 --> | | _| |_ | | <--> P12 |_|15 26|_| A11 --> | | _| |_ | | <--> P13 |_|16 25|_| A12 --> | | _| |_ | | <--> P14 |_|17 24|_| A13 --> | | _| |_ | | <--> P15 |_|18 23|_| A14 --> | | _| |_ | | <--> P16 |_|19 22|_| A15 --> |

| _| |_ | | <--> P17 |_|20 21|_| Vcc Standby | | |______________________| | | | | | | | | | | | | | |Written by Jonathan Bowen | | Programming Research Group | | Oxford University Computing Laboratory | | 8-11 Keble Road | | Oxford OX1 3QD | | England | | | | Tel +44-865-273840 | | | |Created September 1981 | |Updated April 1985 | |Issue 1.5 Copyright (C) J.P.Bowen 1985| ------------------------------------------------------------------------------------------------------------------------------|Mnem. |Op|HINZVC|IEXD#R|Description |Notes | |------+--+------+------+-------------------------+------------| |ABA |1B|*-****|X |Add accumulators |A=A+B | |ABX |3A|------|X |Add registers |X=X+B | |ADCr s|B9|*-****| XXXX |Add with Carry |r=r+s+C | |ADDr s|BB|*-****| XXXX |Add |r=r+s | |ADDD s|F3|--****| XXX* |Add Double accumulator |D=D+s | |ANDr s|B4|--**0-| XXXX |Logical AND |r=r&s | |ASL d|78|--****| XX |Arithmetic Shift Left |d=d*2 | |ASLr |48|--****|X |Arithmetic Shift Left |r=r*2 | |ASLD |05|--****|X |Arithmetic Shift Left |D=D*2 | |ASR d|77|--****| XX |Arithmetic Shift Right |d=d/2 | |ASRr |47|--****|X |Arithmetic Shift Right |r=r/2 | |BCC a|24|------| X|Branch if Carry Clear |If C=0 | |BCS a|25|------| X|Branch if Carry Set |If C=1 | |BEQ a|27|------| X|Branch if Equal |If Z=1 | |BGE a|2C|------| X|Branch if Greater/Equal |If NxV=0 | |BGT a|2E|------| X|Branch if Greater Than |If Zv{NxV}=0| |BHI a|22|------| X|Branch if Higher |If CvZ=0 | |BHS a|24|------| X|Branch if Higher or Same |If C=0 | |BITr s|B5|--**0-| XXXX |Bit Test |r&s | |BLE a|2F|------| X|Branch if Less or Equal |If Zv{NxV}=0| |BLO a|25|------| X|Branch if Lower |If C=1 | |BLS a|23|------| X|Branch if Lower or Same |If CvZ=1 | |BLT a|2D|------| X|Branch if Less Than |If NxV=1 | |BMI a|2B|------| X|Branch if Minus |If N=1 | |BNE a|26|------| X|Branch if Not Equal |If Z=0 | |BPL a|2A|------| X|Branch if Plus |If N=0 | |BRA a|20|------| X|Branch Always |PC=a | |BRN a|21|------| X|Branch Never |No op | |BSR a|8D|------| X|Branch to Subroutine |-[S]=PC,PC=a| |BVC a|28|------| X|Branch if Overflow Clear |If V=0 | |BVS a|29|------| X|Branch if Overflow Set |If V=1 | |CBA |11|--****|X |Compare accumulators |A-B | |CLC |0C|-----0|X |Clear Carry |C=0 |

|CLI |0E|-0----|X |Clear Interrupt Mask |I=0 | |CLR d|7F|--0100| XX |Clear |d=0 | |CLRr |4F|--0100|X |Clear accumulator |r=0 | |CLV |0A|----0-|X |Clear Overflow |V=0 | |CMPr s|B1|--****| XXXX |Compare |r-s | |COM d|63|--**01| XX |Complement |d=~d | |COMr |43|--**01|X |Complement accumulator |r=~r | |CPX s|BC|--****| XXX* |Compare Index Register |X-s | |DAA |19|--****|X |Decimal Adjust Acc. |A=BCD format| |DEC d|7A|--**?-| XX |Decrement |d=d-1 | |DECr |4A|--**?-|X |Decrement accumulator |r=r-1 | |DES |34|------|X |Decrement Stack Pointer |S=S-1 | |DEX |09|---*--|X |Decrement Index Register |X=X-1 | |EORr s|B8|--**0-| XXXX |Logical Exclusive OR |r=rxs | |INC d|7C|--**?-| XX |Increment |d=d+1 | |INCr |4C|--**?-|X |Increment accumulator |r=r+1 | |INS |31|------|X |Increment Stack Pointer |S=S+1 | |INX |08|---*--|X |Increment Index Register |X=X+1 | |JMP d|7E|------| XX |Jump |PC=d | |JSR d|BD|------| XX |Jump to Subroutine |-[S]=PC,PC=d| |LDAr s|B6|--**0-| XXXX |Load Accumulator |r=s | |LDD s|FC|--**0-| XXX* |Load Double accumulator |D=s | |LDS s|BE|--**0-| XXX* |Load Stack Pointer |S=s | |LDX s|FE|--**0-| XXX* |Load Index Register |X=s | |LSR d|74|--0***| XX |Logical Shift Right |d=->{0,d,C} | |LSRr |44|--0***|X |Logical Shift Right |r=->{0,r,C} | |LSRD |04|--0***|X |Logical Shift Right |D=->{0,D,C} | |MUL |3D|-----*|X |Multiply |D=A*B | |NEG d|70|--****| XX |Negate |d=-d | |NEGr |40|--****|X |Negate accumulator |r=-r | |NOP |01|------|X |No Operation | | |ORAr s|BA|--**0-| XXXX |Logical inclusive OR |r=rvs | |PSHA |36|------|X |Push |-[S]=A | |PSHB |37|------|X |Push |-[S]=B | |PSHX |3C|------|X |Push Index Register |-[S]=X | |PULA |32|------|X |Pull |A=[S]+ | |PULB |33|------|X |Pull |B=[S]+ | |PULX |38|------|X |Pull Index Register |X=[S]+ | |ROL d|79|--**?*| XX |Rotate Left |d={C,d}<| |ROLr |49|--**?*|X |Rotate Left accumulator |r={C,r}<| |ROR d|76|--**?*| XX |Rotate Right |d=->{C,d} | |RORr |46|--**?*|X |Rotate Right accumulator |r=->{C,r} | |RTI |3B|??????|X |Return from Interrupt |{regs}=[S]+ | ------------------------------------------------------------------------------------------------------------------------------|Mnem. |Op|HINZVC|IEXD#R|Description |Notes | |------+--+------+------+-+-----------------------+------------| |RTS |39|------|X |Return from Subroutine |PC=[S]+ | |SBA |10|--****|X |Subtract accumulators |A=A-B | |SBCr s|B2|--****| XXXX |Subtract with Carry |r=r-s-C | |SEC |0D|-----1|X |Set Carry |C=1 | |SEI |0F|-1----|X |Set Interrupt Mask |I=1 | |SEV |0B|----1-|X |Set Overflow |V=1 | |STAr d|B7|--**0-| XXX |Store Accumulator |d=r | |STD d|FD|--**0-| XXX |Store Double accumulator |D=r | |STS d|BF|--**0-| XXX |Store Stack Pointer |d=S | |STX d|FF|--**0-| XXX |Store Index Register |d=X | |SUBr s|B0|--****| XXXX |Subtract |r=r-s |

|SUBD s|B3|--****| XXX* |Subtract Double acc. |D=D-s | |SWI |3F|-1----|X |Software Interrupt |-[S]={regs} | |TAB |17|--**0-|X |Transfer accumulators |B=A | |TAP |06|******|X |Transfer |P=A | |TBA |17|--**0-|X |Transfer accumulators |A=B | |TPA |07|------|X |Transfer |A=P | |TST s|7D|--**00| XX |Test |s | |TSTr |4D|--**00|X |Test accumulator |r | |TSX |30|------|X |Transfer |X=S | |TXS |35|------|X |Transfer |S=X | |WAI |3E|-*----|X |Wait for Interrupt |-[S]={regs} | |---------+------+------+--------------------------------------| | CCR |-*01? | |Unaffected/affected/reset/set/unknown | | H |H | |Half carry (Bit 5) | | I | I | |Interrupt mask (Bit 4) | | N | N | |Negative (Bit 3) | | Z | Z | |Zero (Bit 2) | | V | V | |Overflow (Bit 1) | | C | C| |Carry (Bit 0) | |----------------+------+--------------------------------------| | r |I |Inherent (r=A,Op=4XH, r=B,Op=5XH) | | nn,E | E |Extended (Op=E, ~s=e) | | nn,X | X |Index (Op=E-10H, ~s=e+1, JSR ~s=e-1) | | n,D | D |Direct (Op=E-20H, ~s=e-1) | | #n | # |Immediate (8-bit, Op=E-30H, ~s=e-2) | | #nn | * |Immediate (16-bit, Op=E-30H, ~s=e-2) | | a | R|Relative (PC=PC+2+offset) | | r | |Inherent (r=A,Op=BXH, r=B,Op=FXH) | |-----------------------+--------------------------------------| |DIRECT |Direct addressing mode | |EXTEND |Extended addressing mode | |FCB n |Form Constant Byte | |FCC 'string' |Form Constant Characters | |FDB nn |Form Double Byte | |RMB nn |Reserve Memory Bytes | |-----------------------+--------------------------------------| | A |Accumulator A (8-bit, Op=BXH) | | B |Accumulator B (8-bit, Op=FXH) | | D |A and B combined (16-bit, A hi, B lo) | | P |Condition Code Register (8-bit, CCR) | | PC |Program Counter (16-bit) | | S |Stack Pointer (16-bit) | | X |Index Register (16-bit) | |-----------------------+--------------------------------------| | a |Relative address (-125 to +129) | | d s |Destination/source | | n nn |8/16-bit expression (0 to 255/65535) | | r |Accumulator register A or B | | + - * / |Add/subtract/multiply/divide | | & ~ v x |AND/NOT/inclusive OR/exclusive OR | | <- -> |Rotate left/right | | [ ] [ ]+ -[ ] |Indirect address/increment/decrement | | { } {regs} |Combination of operands/{PC,X,A,B,P} | |-----------------------+--------------------------------------| | 0000H to 001FH |Internal registers | | 0080H to 00FFH |128 bytes of internal RAM (not 6803NR)| | FFF0H to FFFFH |Interrupt vectors | | FFF0H to FFF1H |IRQ2 serial I/O interrupt vector |

| FFF2H to FFF3H |IRQ2 timer overflow vector | | FFF4H to FFF5H |IRQ2 timer output compare vector | | FFF6H to FFF7H |IRQ2 timer input capture vector | | FFF8H to FFF9H |IRQ1 interrupt strobe 3 vector | | FFFAH to FFFBH |SWI instruction interrupt vector | | FFFCH to FFFDH |Non-maskable interrupt vector | | FFFEH to FFFFH |Reset vector | ----------------------------------------------------------------