54121-mt----analog Ic Design

NR

Code No: 54121/MT M.Tech. – I Semester Supplementary Examinations, September, 2008 ANALOG IC DESIGN (VLSI System Design) Time: 3hours

Max. Marks:60 Answer any FIVE questions All questions carry equal marks ---

1.a) b) 2.a) b)

Derive an expression for gm of an N-channel MOS FET operating in linear and saturation regions. Give the relative performance of CS, CG, CD amplifiers. Discuss the design aspects of CMOS common source amplifier with diode connected load and derive an expression for the gain. Consider a source follower which is biased by a current mirror. The dimensions of all the transistors are 100 µ m /1.6 µ m, µn Cox = 90µ A / V 2 ,

µ p Cox = 30 µ A / V 2 I bias = 100µ A ,

γ n = 0.5V 1/ 2 , rds − n = 8000 L ( µ m ) / I D ( mA ) .

What is the gain of the stage? 3.a) b)

State the limitations of single stage amplifiers. Explain in detail the design and operation of Wilson current mirror.

4.a)

Deduce the necessary condition that ensures zero input-offset voltage for a 2 stage OP amp. Discuss the trade offs involved in selecting the input stage as pchannel or n-channel with respect to a 2 stage OP amp.

b) 5.)

Discuss in detail the compensation of OP amp that makes it completely independent of process and temperature variations.

6.a) b)

Give the significance of CMFB circuits. Give an account of charge injection errors in connection with comparators and suggest a method to minimize the same.

Contd…2

Code No: 54121/MT 7.a)

b) 8.a) b)

::2::

Explain the following in the context of data converters: i) Resolution ii) Offset and gain error iii) Accuracy iv) Integral non linearity error v) Missing codes Explain briefly a 3 bit flash A/D converter. State the salient issues in designing Flash A/D converters. Discuss in detail the nois shaped delta sigma modulator. Write an account of band pass over sampling converters. *****