54111 Mt Digital System Design

Code No: 54111/MT M.Tech. I-Semester Examinations, February-2007. DIGITAL SYSTEM DESIGN (Digital System and Computer Electronics, Digital Electronics and Communication Systems, VLSI System Design) Time: 3 hours Max. Marks: 60 Answer any FIVE questions All questions carry equal marks --1.a) What is a logic probe what for it is used and list different internal digital IC faults? b) What are the most common type of external faults? 2.a) b) 3.a) b)

Develop an ASM chart of D flip flop and realize it using only NAND Gates. Discuss in detail about reduction of state tables and state assignments. Explain about the following types of faults: (i) stuck at faults (ii) Bridge faults (iii) temporary faults Draw the circuit which realizes the function f(x) = x1x2 + x3 x4 using AND-OR gates using Boolean difference method obtain the test set to detect SAo fault on input line x1 of the circuit.

4.a) b)

Describe the algorithmic steps involved in PODEM. With an example, explain the transition count testing method.

5.a) b)

Distinguish between Mealy and Moore machines. Convert the following Mealy machine into a corresponding Moore machine. PS A B,O E,O B E,O D,O C D,I A,O D C,I E,O E B,O D,O

6.a) b)

Describe the advantages of PLA minimization and folding. Design a 3 bit BCD to grey code converter and realize the circuit using PLA and then show that how folding will reduce the number of cross points given on the PLA.

7.a)

With examples, explain in detail about various types of cross point fault that occur in PLAs. With an example, explain how test generation can be achieved in testing a PLA.

b) 8.a) b)

Explain the following with examples: (i) flow table (ii) state reduction. With respect to an asynchronous sequential machine, explain about minimal closed corners. ---