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Case 5:05-cv-00334-RMW
Document 2066-2
Filed 08/19/2008
EXHIBIT A
Page 1 of 10
Case 5:05-cv-00334-RMW
1 2 3 4 5
Document 2066-2
Filed 08/19/2008
Gregory P. Stone (State Bar No. 078329) Steven M. Perry (State Bar No. 106154) Sean Eskovitz (State Bar No. 241877) MUNGER, TOLLES & OLSON LLP 355 South Grand Avenue, 35th Floor Los Angeles, California 90071-1560 Telephone: (213) 683-9100 Facsimile: (213) 687-3702 Email: [email protected]; [email protected]; [email protected]
Rollin A. Ransom (State Bar No. 196126) SIDLEY AUSTIN LLP 555 West Fifth Street, Suite 4000 Los Angeles, California 90013-1010 Telephone: (213) 896-6000 Facsimile: (213) 896-6600 Email: [email protected]
6
11
Peter A. Detre (State Bar No. 182619) Carolyn Hoecker Luedtke (State Bar No. 207976) Jennifer L. Polse (State Bar No. 219202) MUNGER, TOLLES & OLSON LLP 560 Mission Street, 27th Floor San Francisco, California 94105 Telephone: (415) 512-4000 Facsimile: (415) 512-4077 Email: [email protected]; [email protected]; [email protected]
12
Attorneys for RAMBUS INC.
7 8 9 10
Page 2 of 10
Pierre J. Hubert (Pro Hac Vice) Craig N. Tolliver (Pro Hac Vice) McKOOL SMITH PC 300 West 6th Street, Suite 1700 Austin, Texas 78701 Telephone: (512) 692-8700 Facsimile: (512) 692-8744 Email: [email protected]; [email protected]
13
UNITED STATES DISTRICT COURT
14
NORTHERN DISTRICT OF CALIFORNIA, SAN JOSE DIVISION
15 16
RAMBUS INC., Plaintiff,
17 18 19
vs.
22
RAMBUS INC.’S MOTION FOR RECONSIDERATION OF CLAIM CONSTRUCTION ORDER FOR THE FARMWALD/HOROWITZ PATENTS
HYNIX SEMICONDUCTOR INC., et al., Defendants.
20 21
CASE NO.: C 05-00334 RMW
RAMBUS INC.,
CASE NO. C 05-02298 RMW Plaintiff,
v.
23 24 25
SAMSUNG ELECTRONICS CO., LTD., et al., Defendants.
26 27 28 RAMBUS’S MOTION FOR RECONSIDERATION C 05-00334 RMW; C 05-02298 RMW; C 06-00244 RMW
Case 5:05-cv-00334-RMW
Document 2066-2
Filed 08/19/2008
Page 3 of 10
1 2
CASE NO.: C 06-00244 RMW RAMBUS INC.,
3 Plaintiff, 4 vs. 5 MICRON TECHNOLOGY INC., et al, 6 Defendants. 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 RAMBUS’S MOTION FOR RECONSIDERATION C 05-00334 RMW; C 05-02298 RMW; C 06-00244 RMW
Case 5:05-cv-00334-RMW
1
I.
Document 2066-2
Filed 08/19/2008
Page 4 of 10
INTRODUCTION Rambus moves for reconsideration of the Court’s construction of the term
2 3
“memory device.” The Court adopted the Manufacturers’ proposed construction of the term as “a
4
device in which information can be stored and retrieved electronically” and expressly stated that
5
“[i]t need not be on a single chip.” Claim Construction Order for the Farmwald/Horowitz
6
Patents, 7/10/08 (“Order”), at 34. In so doing, however, the Court appears to have misunderstood
7
or overlooked key evidence that cannot be squared with the Court’s construction. As set forth
8
below, intrinsic evidence from the specification and prosecution history of the
9
Farmwald/Horowitz patents, as well as extrinsic evidence, establish that a “memory device,” as
10
used in the asserted claims, is a single chip. Indeed, as the evidence makes clear, enabling high-
11
speed access to large blocks of data from a single memory chip is the essence of the
12
Farmwald/Horowitz inventions. In the Order, the Court conjectured that the Manufacturers were seeking to remove
13 14
the single chip limitation from “integrated circuit device” in order to bolster their invalidity
15
arguments. Order at 31. This is precisely what the Manufacturers hoped to accomplish by
16
proposing broad constructions of “integrated circuit device” and “memory device” that were not
17
limited to a single chip. In fact, the Manufacturers are asserting various prior art references
18
containing multiple chips (such as the bus interface unit and memory array in the Jackson patent,
19
discussed below) that, the Manufacturers argue, together satisfy the limitations of Rambus’s
20
patent claims.1 Construing “memory device” without a single chip limitation, as the Court has
21
done, provides the Manufacturers with the opportunity to argue that certain claims drawn to a
22
memory device are anticipated by these multi-chip prior art references. However, as the
23
specification and the prosecution history show, it was precisely this sort of prior art that Drs.
24
1
25 26 27 28
The Manufacturers are asserting other, similar, prior art as well. For example, as in Hynix I, the Manufacturers are asserting that the combinations of memory controllers and large memory arrays in both the Budde and CVAX references invalidate the claims, despite the fact that they involve standard, asynchronous prior art DRAMs that do not themselves satisfy the claim limitations. See Hynix I Patent Trial, Tr. (4/6/06) (Murphy) at 2519:8 – 2521:22; 2530:14 – 2534:8. The CVAX reference, for example, consists of a memory controller combined with a separate memory card containing over 100 asynchronous DRAM chips. Id., Tr. (4/10/06) (Murphy) at 2632:3-16. -1-
RAMBUS’S MOTION FOR RECONSIDERATION C 05-00334 RMW; C 05-02298 RMW; C 06-00244 RMW
Case 5:05-cv-00334-RMW
1
Document 2066-2
Filed 08/19/2008
Page 5 of 10
Farmwald and Horowitz were seeking to improve through their inventions.
2
The evidence shows that a “memory device,” as used in the Farmwald/Horowitz
3
patents, is a single chip, and it would be contrary to that evidence to allow the Manufacturers to
4
argue that prior art requiring multiple chips anticipate the Farmwald/Horowitz inventions.
5
Consequently, Rambus urges the Court to find that “memory device” should properly be
6
construed as a single chip.
7
II.
8
DISCUSSION A.
9
The Court’s Construction of “Memory Device” Is At Odds With the Evidence. 1.
10 11
The Court’s Construction of “Memory Device” Is Contradicted By The Specification.
In its Order, the Court cites the statement in the patent specification that “one
12
object of the present invention is to use a new bus interface built into semiconductor devices to
13
support high-speed access to large blocks of data from a single memory device by an external
14
user of the data, such as a microprocessor, in an efficient and cost-effective manner.” Order at
15
33. But the Court then notes that “[i]t is unclear why this sentence would compel a person of
16
ordinary skill in the art to interpret a ‘memory device’ as residing on a single chip.” Id. The
17
reason why this sentence compels such an interpretation becomes clear when it is considered in
18
the context of the state of the art at the time Drs. Farmwald and Horowitz filed their patent
19
application.
20
A person of ordinary skill in the art would understand that, at the time of the filing
21
of the original Rambus patent application, computer memory generally consisted of memory
22
cards containing multiple chips. As Dr. Horowitz explained during his testimony at the Conduct
23
Trial:
24
So, you know, if you think way back to almost 20 years ago now
25
when people built systems, you had a card that was like the
26
processor, it had multiple chips on it, and you had a card which was
27
your memory and it had multiple chips and they often
28
communicat[ed] over some bus, some collection of wires. -2-
RAMBUS’S MOTION FOR RECONSIDERATION C 05-00334 RMW; C 05-02298 RMW; C 06-00244 RMW
Case 5:05-cv-00334-RMW
Document 2066-2
Filed 08/19/2008
Page 6 of 10
1
Tr. (3/05/08) at 4091:23 – 4092:4. Undisputed testimony shows that the essence of the inventions
2
made by Drs. Farmwald and Horowitz is to improve the performance of memory chips to such an
3
extent that a single chip could take the place of the large memory cards of the time. See Tr.
4
(3/5/08) at 4092:5-9 (Horowitz) (“And Mike's observation was, well, look, in the future we're not
5
going to be plugging in memory cards, we're going to be plugging in memory chips, and,
6
therefore, we have to really change the whole interface to the DRAM . . . .”); Tr. (3/20/08) at
7
5502:13-18(Farmwald) (explaining that inventions involved “put[ting] more, I'll call it
8
complexity, more functionality into the memory chip so that the memory chip [was] sufficiently
9
smart enough that you could connect a single memory chip to a processor and have it do
10 11
[something] useful.”). In this context, a person of skill in the art would understand that when the
12
specification referred to an object of the invention as supporting “high-speed access to large
13
blocks of data from a single memory device,” the term “memory device” could not refer to the
14
memory cards containing multiple memory chips that would be required for high speed access to
15
large blocks of data in the prior art. As an initial matter, if a memory device could consist of any
16
number of chips, then it would make little sense to modify the term “memory device” with
17
“single” because, under the Court’s construction, “single” would not in any way limit what the
18
memory device could be – it is unclear from the Court’s construction where one would draw the
19
line between what could and could not be a “memory device” and the Manufacturers will feel free
20
to argue that it could consist of prior art devices including 10 chips, or 50 chips, or 100 chips.
21
Essentially, if a memory device could consist of any number of chips and any type
22
of chip – thereby encompassing memory cards with multiple memory chips and additional logic
23
chips, and, perhaps, even memory arrays with multiple memory cards – then a person of ordinary
24
skill in the art would understand that it would be no invention to allow high-speed access to large
25
blocks of data from a single memory device. If the user wished to access larger blocks of data
26
without compromising speed, all that would need to be done would be to add larger memory
27
cards with more memory chips operating in parallel, or additional memory cards. There would
28
be no bound on the amount of data that could be obtained from any prior art memory chips, by -3-
RAMBUS’S MOTION FOR RECONSIDERATION C 05-00334 RMW; C 05-02298 RMW; C 06-00244 RMW
Case 5:05-cv-00334-RMW
Document 2066-2
Filed 08/19/2008
Page 7 of 10
1
simply adding more and more of them and calling the resulting mass of chips a “single memory
2
device.” This situation, according to which one had to add more and more memory chips to a
3
system in order to provide sufficient data for high-speed operation, was precisely the prior art that
4
the Rambus inventors were trying to improve by allowing for high speed access to large blocks of
5
data from a single memory chip.2
6
A person of ordinary skill in the art would understand that Rambus’s inventions, as
7
disclosed in the specification, related to obtaining high-speed access to large blocks of data from
8
single-chip memory devices. The Court should reconsider its construction of “memory device” to
9
reflect this understanding.
10
2.
11
The Court Did Not Address Clear Evidence In the Prosecution History Showing that a “Memory Device” Is a Single Chip.
In its Order, the Court does not discuss the prosecution history plainly showing 12 that “memory device” is to be interpreted as a single chip. See Rambus’s Reply to 13 Manufacturers’ Responsive Brief on Claim Construction, at 10. During prosecution of Rambus’s 14 patent no. 6,034,918 – one of the patents-in-suit in Hynix I that is in the chain leading to certain of 15 the patents-in-suit in these coordinated cases – the examiner rejected claims drawn to “memory 16 devices” based on U.S. patent no. 4,315,308 issued to Jackson (the “Jackson patent”). The 17 examiner concluded that the Jackson patent anticipated the claims because a so-called “bus 18 interface unit” in Jackson, if combined with the memory array, contained all the claim limitations, 19 such as receiving block size information. See Declaration of Pierre J. Hubert in Support of 20 Rambus’s Reply to Manufacturers’ Responsive Brief on Claim Construction, 9/28/07, Ex. 6 21 22 23 24 25 26 27 28
2
That the statement “high-speed access to large blocks of data from a single memory device” in the specification refers to a single memory chip, is confirmed by other portions of the specification. For example, the Field of the Invention in the specification of the Farmwald/Horowitz patents refers to “high speed transfer of blocks of data, particularly to and from memory devices, with reduced power consumption.” See U.S. Patent No. 6,182,184, col. 1:23-25. A person of skill in the art would understand that such reduced power consumption could only be obtained by accessing the blocks of data on a single memory chip, rather than from multiple memory chips as in prior art systems. See id., col. 17:18-25 (“By using a single row access in a single RAM to supply all the bits for a block request (compared to a row-access in each of multiple RAMs in conventional memory systems) the power per bit can be made very small. Since the power dissipated by memory devices using this invention is significantly reduced, the devices potentially can be placed much closer together than with conventional designs.”) (Emphasis added.) -4-
RAMBUS’S MOTION FOR RECONSIDERATION C 05-00334 RMW; C 05-02298 RMW; C 06-00244 RMW
Case 5:05-cv-00334-RMW
Document 2066-2
Filed 08/19/2008
Page 8 of 10
1
(Amendment, 7/23/99, at 9-13 (citing 7/16/99 Office Action)). Thus, the examiner’s initial
2
rejection was based on the premise that a “memory device” could consist of multiple chips –
3
namely, the memory chips in the memory array combined with the separate bus interface unit in
4
Jackson.
5
In response to the claim rejection, Rambus made clear that “memory device,” as
6
that term is used in its patent claims, refers to a single memory chip. Rambus pointed out that, in
7
the Jackson patent, certain claim limitations were arguably satisfied by the bus interface unit, but
8
not by the “memory devices.” For example, Rambus argued that, in Jackson, the data length
9
transfer information, which the examiner had found corresponded to the block size information
10
required by the claims at issue, was received by the bus interface unit, not the memory devices:
11
[T]he data length transfer information in Jackson is not provided to
12
the memory devices. Instead, the bus interface unit receives and
13
decodes that information . . .”
14
Id. at 11-12 (emphasis added). Likewise, Rambus argued that “the memory devices employed in
15
Jackson did not provide data synchronously with respect to the clock signal,” as required by the
16
claims, but, rather, the bus interface unit provided that function. Id. at 12. Of course, these
17
arguments would have been nonsensical if the “memory device” could consist of multiple chips
18
and, thus, include the bus interface unit. Because the bus interface unit in the Jackson patent does
19
receive the data length transfer information and does provide data synchronously with respect to
20
the clock signal, Rambus could hardly have argued that the memory devices did not satisfy these
21
limitations if the bus interface unit could be part of the memory device.3
22
In response to Rambus’s arguments, the examiner allowed Rambus’s claims. The
23
examiner thus allowed Rambus’s claims based on the understanding that “memory device,” as
24
used therein, could not refer to multiple chips, such as a memory array combined with a bus
25
3
26 27 28
In addition to making clear that a “memory device,” as used in Rambus’s claims, could not include a separate chip, such as a bus interface unit, Rambus’s response also demonstrated that, such a memory device was a single memory chip and did not include multiple memory chips joined together to form a memory module. See id. at 10 (referring to the Jackson patent’s “memory devices, and modules containing those devices”); id. (referring to “memory devices” and “memory modules incorporating such devices”). -5-
RAMBUS’S MOTION FOR RECONSIDERATION C 05-00334 RMW; C 05-02298 RMW; C 06-00244 RMW
Case 5:05-cv-00334-RMW
Document 2066-2
Filed 08/19/2008
Page 9 of 10
1
interface unit, as in the Jackson patent. Now, the Manufacturers are asserting as prior art the
2
Jackson patent itself – as well as other similar references – to claim that the bus interface unit and
3
memory array of Jackson are, together, a “memory device” anticipating the claims of certain
4
Farmwald/Horowitz patents. In other words, the Manufacturers’ argument is identical to the basis
5
for the examiner’s initial rejection that was overcome by Rambus making clear that “memory
6
device,” as used in the patents, cannot refer to the combination of a bus interface unit and a
7
memory array. Indeed, if Rambus were now to try to claim such a broad construction of
8
“memory device,” it would be precluded from doing so by the prosecution history.
9
The Manufacturers have no response to the prosecution history of the ’918 patent –
10
in the lineage of certain of the asserted patents and, hence, part of the prosecution history of those
11
patents – plainly showing that a “memory device” cannot consist of multiple chips. However,
12
the Court’s construction does not preclude the Manufacturers from designating some arbitrary
13
collection of chips in prior art systems as a “memory device” and arguing that it anticipates
14
certain claims of the Farmwald/Horowitz patents. In light of the prosecution history to the
15
contrary, the Court should reconsider it construction of “memory device” and hold that it refers to
16
a single memory chip in the claims of the patents-in-suit.
17 18 19
3.
The Court Does Not Address the Evidence Showing that Persons of Skill in the Art Would Not Consider the Term “Memory Device” to Refer to Multiple Chips.
The Court’s claim construction order also does not address key extrinsic evidence
20
that Rambus had brought to the Court’s attention. In particular, one of the Manufacturers own
21
experts has admitted that a person of skill in the art would not consider the term “memory device”
22
to refer to multiple-chip devices. See Rambus’s Reply to Manufacturers’ Responsive Brief on
23
Claim Construction, at 11. In his testimony in an unrelated interference action, Mr. Rhoden was
24
asked whether “a card that has multiple package memory chips [is] a memory device?” Id. at 11,
25
n.17. Mr. Rhoden candidly responded: “Is a – no. Typically not.” Id. This admission by Mr.
26
Rhoden, who clearly has no incentive to color his testimony in Rambus’s favor, is highly
27
persuasive evidence that the term “memory device” is not considered by persons of skill in the art
28
to include multiple chips. -6-
RAMBUS’S MOTION FOR RECONSIDERATION C 05-00334 RMW; C 05-02298 RMW; C 06-00244 RMW
Case 5:05-cv-00334-RMW
1 2
III.
Document 2066-2
Filed 08/19/2008
Page 10 of 10
CONCLUSION For the reasons set forth above, Rambus respectfully requests that the Court
3
construe “memory device,” as used in the asserted claims of the Farmwald/Horowitz patents, as
4
being restricted to a single chip.
5 DATED: August 19, 2008
MUNGER, TOLLES & OLSON LLP
6 SIDLEY AUSTIN LLP 7 McKOOL SMITH P.C. 8 9 By: 10 11
/s/ Peter A. Detre PETER A. DETRE
Attorneys for RAMBUS INC.
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 -7-
RAMBUS’S MOTION FOR RECONSIDERATION C 05-00334 RMW; C 05-02298 RMW; C 06-00244 RMW
Document 2066-2
Filed 08/19/2008
EXHIBIT A
Page 1 of 10
Case 5:05-cv-00334-RMW
1 2 3 4 5
Document 2066-2
Filed 08/19/2008
Gregory P. Stone (State Bar No. 078329) Steven M. Perry (State Bar No. 106154) Sean Eskovitz (State Bar No. 241877) MUNGER, TOLLES & OLSON LLP 355 South Grand Avenue, 35th Floor Los Angeles, California 90071-1560 Telephone: (213) 683-9100 Facsimile: (213) 687-3702 Email: [email protected]; [email protected]; [email protected]
Rollin A. Ransom (State Bar No. 196126) SIDLEY AUSTIN LLP 555 West Fifth Street, Suite 4000 Los Angeles, California 90013-1010 Telephone: (213) 896-6000 Facsimile: (213) 896-6600 Email: [email protected]
6
11
Peter A. Detre (State Bar No. 182619) Carolyn Hoecker Luedtke (State Bar No. 207976) Jennifer L. Polse (State Bar No. 219202) MUNGER, TOLLES & OLSON LLP 560 Mission Street, 27th Floor San Francisco, California 94105 Telephone: (415) 512-4000 Facsimile: (415) 512-4077 Email: [email protected]; [email protected]; [email protected]
12
Attorneys for RAMBUS INC.
7 8 9 10
Page 2 of 10
Pierre J. Hubert (Pro Hac Vice) Craig N. Tolliver (Pro Hac Vice) McKOOL SMITH PC 300 West 6th Street, Suite 1700 Austin, Texas 78701 Telephone: (512) 692-8700 Facsimile: (512) 692-8744 Email: [email protected]; [email protected]
13
UNITED STATES DISTRICT COURT
14
NORTHERN DISTRICT OF CALIFORNIA, SAN JOSE DIVISION
15 16
RAMBUS INC., Plaintiff,
17 18 19
vs.
22
RAMBUS INC.’S MOTION FOR RECONSIDERATION OF CLAIM CONSTRUCTION ORDER FOR THE FARMWALD/HOROWITZ PATENTS
HYNIX SEMICONDUCTOR INC., et al., Defendants.
20 21
CASE NO.: C 05-00334 RMW
RAMBUS INC.,
CASE NO. C 05-02298 RMW Plaintiff,
v.
23 24 25
SAMSUNG ELECTRONICS CO., LTD., et al., Defendants.
26 27 28 RAMBUS’S MOTION FOR RECONSIDERATION C 05-00334 RMW; C 05-02298 RMW; C 06-00244 RMW
Case 5:05-cv-00334-RMW
Document 2066-2
Filed 08/19/2008
Page 3 of 10
1 2
CASE NO.: C 06-00244 RMW RAMBUS INC.,
3 Plaintiff, 4 vs. 5 MICRON TECHNOLOGY INC., et al, 6 Defendants. 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 RAMBUS’S MOTION FOR RECONSIDERATION C 05-00334 RMW; C 05-02298 RMW; C 06-00244 RMW
Case 5:05-cv-00334-RMW
1
I.
Document 2066-2
Filed 08/19/2008
Page 4 of 10
INTRODUCTION Rambus moves for reconsideration of the Court’s construction of the term
2 3
“memory device.” The Court adopted the Manufacturers’ proposed construction of the term as “a
4
device in which information can be stored and retrieved electronically” and expressly stated that
5
“[i]t need not be on a single chip.” Claim Construction Order for the Farmwald/Horowitz
6
Patents, 7/10/08 (“Order”), at 34. In so doing, however, the Court appears to have misunderstood
7
or overlooked key evidence that cannot be squared with the Court’s construction. As set forth
8
below, intrinsic evidence from the specification and prosecution history of the
9
Farmwald/Horowitz patents, as well as extrinsic evidence, establish that a “memory device,” as
10
used in the asserted claims, is a single chip. Indeed, as the evidence makes clear, enabling high-
11
speed access to large blocks of data from a single memory chip is the essence of the
12
Farmwald/Horowitz inventions. In the Order, the Court conjectured that the Manufacturers were seeking to remove
13 14
the single chip limitation from “integrated circuit device” in order to bolster their invalidity
15
arguments. Order at 31. This is precisely what the Manufacturers hoped to accomplish by
16
proposing broad constructions of “integrated circuit device” and “memory device” that were not
17
limited to a single chip. In fact, the Manufacturers are asserting various prior art references
18
containing multiple chips (such as the bus interface unit and memory array in the Jackson patent,
19
discussed below) that, the Manufacturers argue, together satisfy the limitations of Rambus’s
20
patent claims.1 Construing “memory device” without a single chip limitation, as the Court has
21
done, provides the Manufacturers with the opportunity to argue that certain claims drawn to a
22
memory device are anticipated by these multi-chip prior art references. However, as the
23
specification and the prosecution history show, it was precisely this sort of prior art that Drs.
24
1
25 26 27 28
The Manufacturers are asserting other, similar, prior art as well. For example, as in Hynix I, the Manufacturers are asserting that the combinations of memory controllers and large memory arrays in both the Budde and CVAX references invalidate the claims, despite the fact that they involve standard, asynchronous prior art DRAMs that do not themselves satisfy the claim limitations. See Hynix I Patent Trial, Tr. (4/6/06) (Murphy) at 2519:8 – 2521:22; 2530:14 – 2534:8. The CVAX reference, for example, consists of a memory controller combined with a separate memory card containing over 100 asynchronous DRAM chips. Id., Tr. (4/10/06) (Murphy) at 2632:3-16. -1-
RAMBUS’S MOTION FOR RECONSIDERATION C 05-00334 RMW; C 05-02298 RMW; C 06-00244 RMW
Case 5:05-cv-00334-RMW
1
Document 2066-2
Filed 08/19/2008
Page 5 of 10
Farmwald and Horowitz were seeking to improve through their inventions.
2
The evidence shows that a “memory device,” as used in the Farmwald/Horowitz
3
patents, is a single chip, and it would be contrary to that evidence to allow the Manufacturers to
4
argue that prior art requiring multiple chips anticipate the Farmwald/Horowitz inventions.
5
Consequently, Rambus urges the Court to find that “memory device” should properly be
6
construed as a single chip.
7
II.
8
DISCUSSION A.
9
The Court’s Construction of “Memory Device” Is At Odds With the Evidence. 1.
10 11
The Court’s Construction of “Memory Device” Is Contradicted By The Specification.
In its Order, the Court cites the statement in the patent specification that “one
12
object of the present invention is to use a new bus interface built into semiconductor devices to
13
support high-speed access to large blocks of data from a single memory device by an external
14
user of the data, such as a microprocessor, in an efficient and cost-effective manner.” Order at
15
33. But the Court then notes that “[i]t is unclear why this sentence would compel a person of
16
ordinary skill in the art to interpret a ‘memory device’ as residing on a single chip.” Id. The
17
reason why this sentence compels such an interpretation becomes clear when it is considered in
18
the context of the state of the art at the time Drs. Farmwald and Horowitz filed their patent
19
application.
20
A person of ordinary skill in the art would understand that, at the time of the filing
21
of the original Rambus patent application, computer memory generally consisted of memory
22
cards containing multiple chips. As Dr. Horowitz explained during his testimony at the Conduct
23
Trial:
24
So, you know, if you think way back to almost 20 years ago now
25
when people built systems, you had a card that was like the
26
processor, it had multiple chips on it, and you had a card which was
27
your memory and it had multiple chips and they often
28
communicat[ed] over some bus, some collection of wires. -2-
RAMBUS’S MOTION FOR RECONSIDERATION C 05-00334 RMW; C 05-02298 RMW; C 06-00244 RMW
Case 5:05-cv-00334-RMW
Document 2066-2
Filed 08/19/2008
Page 6 of 10
1
Tr. (3/05/08) at 4091:23 – 4092:4. Undisputed testimony shows that the essence of the inventions
2
made by Drs. Farmwald and Horowitz is to improve the performance of memory chips to such an
3
extent that a single chip could take the place of the large memory cards of the time. See Tr.
4
(3/5/08) at 4092:5-9 (Horowitz) (“And Mike's observation was, well, look, in the future we're not
5
going to be plugging in memory cards, we're going to be plugging in memory chips, and,
6
therefore, we have to really change the whole interface to the DRAM . . . .”); Tr. (3/20/08) at
7
5502:13-18(Farmwald) (explaining that inventions involved “put[ting] more, I'll call it
8
complexity, more functionality into the memory chip so that the memory chip [was] sufficiently
9
smart enough that you could connect a single memory chip to a processor and have it do
10 11
[something] useful.”). In this context, a person of skill in the art would understand that when the
12
specification referred to an object of the invention as supporting “high-speed access to large
13
blocks of data from a single memory device,” the term “memory device” could not refer to the
14
memory cards containing multiple memory chips that would be required for high speed access to
15
large blocks of data in the prior art. As an initial matter, if a memory device could consist of any
16
number of chips, then it would make little sense to modify the term “memory device” with
17
“single” because, under the Court’s construction, “single” would not in any way limit what the
18
memory device could be – it is unclear from the Court’s construction where one would draw the
19
line between what could and could not be a “memory device” and the Manufacturers will feel free
20
to argue that it could consist of prior art devices including 10 chips, or 50 chips, or 100 chips.
21
Essentially, if a memory device could consist of any number of chips and any type
22
of chip – thereby encompassing memory cards with multiple memory chips and additional logic
23
chips, and, perhaps, even memory arrays with multiple memory cards – then a person of ordinary
24
skill in the art would understand that it would be no invention to allow high-speed access to large
25
blocks of data from a single memory device. If the user wished to access larger blocks of data
26
without compromising speed, all that would need to be done would be to add larger memory
27
cards with more memory chips operating in parallel, or additional memory cards. There would
28
be no bound on the amount of data that could be obtained from any prior art memory chips, by -3-
RAMBUS’S MOTION FOR RECONSIDERATION C 05-00334 RMW; C 05-02298 RMW; C 06-00244 RMW
Case 5:05-cv-00334-RMW
Document 2066-2
Filed 08/19/2008
Page 7 of 10
1
simply adding more and more of them and calling the resulting mass of chips a “single memory
2
device.” This situation, according to which one had to add more and more memory chips to a
3
system in order to provide sufficient data for high-speed operation, was precisely the prior art that
4
the Rambus inventors were trying to improve by allowing for high speed access to large blocks of
5
data from a single memory chip.2
6
A person of ordinary skill in the art would understand that Rambus’s inventions, as
7
disclosed in the specification, related to obtaining high-speed access to large blocks of data from
8
single-chip memory devices. The Court should reconsider its construction of “memory device” to
9
reflect this understanding.
10
2.
11
The Court Did Not Address Clear Evidence In the Prosecution History Showing that a “Memory Device” Is a Single Chip.
In its Order, the Court does not discuss the prosecution history plainly showing 12 that “memory device” is to be interpreted as a single chip. See Rambus’s Reply to 13 Manufacturers’ Responsive Brief on Claim Construction, at 10. During prosecution of Rambus’s 14 patent no. 6,034,918 – one of the patents-in-suit in Hynix I that is in the chain leading to certain of 15 the patents-in-suit in these coordinated cases – the examiner rejected claims drawn to “memory 16 devices” based on U.S. patent no. 4,315,308 issued to Jackson (the “Jackson patent”). The 17 examiner concluded that the Jackson patent anticipated the claims because a so-called “bus 18 interface unit” in Jackson, if combined with the memory array, contained all the claim limitations, 19 such as receiving block size information. See Declaration of Pierre J. Hubert in Support of 20 Rambus’s Reply to Manufacturers’ Responsive Brief on Claim Construction, 9/28/07, Ex. 6 21 22 23 24 25 26 27 28
2
That the statement “high-speed access to large blocks of data from a single memory device” in the specification refers to a single memory chip, is confirmed by other portions of the specification. For example, the Field of the Invention in the specification of the Farmwald/Horowitz patents refers to “high speed transfer of blocks of data, particularly to and from memory devices, with reduced power consumption.” See U.S. Patent No. 6,182,184, col. 1:23-25. A person of skill in the art would understand that such reduced power consumption could only be obtained by accessing the blocks of data on a single memory chip, rather than from multiple memory chips as in prior art systems. See id., col. 17:18-25 (“By using a single row access in a single RAM to supply all the bits for a block request (compared to a row-access in each of multiple RAMs in conventional memory systems) the power per bit can be made very small. Since the power dissipated by memory devices using this invention is significantly reduced, the devices potentially can be placed much closer together than with conventional designs.”) (Emphasis added.) -4-
RAMBUS’S MOTION FOR RECONSIDERATION C 05-00334 RMW; C 05-02298 RMW; C 06-00244 RMW
Case 5:05-cv-00334-RMW
Document 2066-2
Filed 08/19/2008
Page 8 of 10
1
(Amendment, 7/23/99, at 9-13 (citing 7/16/99 Office Action)). Thus, the examiner’s initial
2
rejection was based on the premise that a “memory device” could consist of multiple chips –
3
namely, the memory chips in the memory array combined with the separate bus interface unit in
4
Jackson.
5
In response to the claim rejection, Rambus made clear that “memory device,” as
6
that term is used in its patent claims, refers to a single memory chip. Rambus pointed out that, in
7
the Jackson patent, certain claim limitations were arguably satisfied by the bus interface unit, but
8
not by the “memory devices.” For example, Rambus argued that, in Jackson, the data length
9
transfer information, which the examiner had found corresponded to the block size information
10
required by the claims at issue, was received by the bus interface unit, not the memory devices:
11
[T]he data length transfer information in Jackson is not provided to
12
the memory devices. Instead, the bus interface unit receives and
13
decodes that information . . .”
14
Id. at 11-12 (emphasis added). Likewise, Rambus argued that “the memory devices employed in
15
Jackson did not provide data synchronously with respect to the clock signal,” as required by the
16
claims, but, rather, the bus interface unit provided that function. Id. at 12. Of course, these
17
arguments would have been nonsensical if the “memory device” could consist of multiple chips
18
and, thus, include the bus interface unit. Because the bus interface unit in the Jackson patent does
19
receive the data length transfer information and does provide data synchronously with respect to
20
the clock signal, Rambus could hardly have argued that the memory devices did not satisfy these
21
limitations if the bus interface unit could be part of the memory device.3
22
In response to Rambus’s arguments, the examiner allowed Rambus’s claims. The
23
examiner thus allowed Rambus’s claims based on the understanding that “memory device,” as
24
used therein, could not refer to multiple chips, such as a memory array combined with a bus
25
3
26 27 28
In addition to making clear that a “memory device,” as used in Rambus’s claims, could not include a separate chip, such as a bus interface unit, Rambus’s response also demonstrated that, such a memory device was a single memory chip and did not include multiple memory chips joined together to form a memory module. See id. at 10 (referring to the Jackson patent’s “memory devices, and modules containing those devices”); id. (referring to “memory devices” and “memory modules incorporating such devices”). -5-
RAMBUS’S MOTION FOR RECONSIDERATION C 05-00334 RMW; C 05-02298 RMW; C 06-00244 RMW
Case 5:05-cv-00334-RMW
Document 2066-2
Filed 08/19/2008
Page 9 of 10
1
interface unit, as in the Jackson patent. Now, the Manufacturers are asserting as prior art the
2
Jackson patent itself – as well as other similar references – to claim that the bus interface unit and
3
memory array of Jackson are, together, a “memory device” anticipating the claims of certain
4
Farmwald/Horowitz patents. In other words, the Manufacturers’ argument is identical to the basis
5
for the examiner’s initial rejection that was overcome by Rambus making clear that “memory
6
device,” as used in the patents, cannot refer to the combination of a bus interface unit and a
7
memory array. Indeed, if Rambus were now to try to claim such a broad construction of
8
“memory device,” it would be precluded from doing so by the prosecution history.
9
The Manufacturers have no response to the prosecution history of the ’918 patent –
10
in the lineage of certain of the asserted patents and, hence, part of the prosecution history of those
11
patents – plainly showing that a “memory device” cannot consist of multiple chips. However,
12
the Court’s construction does not preclude the Manufacturers from designating some arbitrary
13
collection of chips in prior art systems as a “memory device” and arguing that it anticipates
14
certain claims of the Farmwald/Horowitz patents. In light of the prosecution history to the
15
contrary, the Court should reconsider it construction of “memory device” and hold that it refers to
16
a single memory chip in the claims of the patents-in-suit.
17 18 19
3.
The Court Does Not Address the Evidence Showing that Persons of Skill in the Art Would Not Consider the Term “Memory Device” to Refer to Multiple Chips.
The Court’s claim construction order also does not address key extrinsic evidence
20
that Rambus had brought to the Court’s attention. In particular, one of the Manufacturers own
21
experts has admitted that a person of skill in the art would not consider the term “memory device”
22
to refer to multiple-chip devices. See Rambus’s Reply to Manufacturers’ Responsive Brief on
23
Claim Construction, at 11. In his testimony in an unrelated interference action, Mr. Rhoden was
24
asked whether “a card that has multiple package memory chips [is] a memory device?” Id. at 11,
25
n.17. Mr. Rhoden candidly responded: “Is a – no. Typically not.” Id. This admission by Mr.
26
Rhoden, who clearly has no incentive to color his testimony in Rambus’s favor, is highly
27
persuasive evidence that the term “memory device” is not considered by persons of skill in the art
28
to include multiple chips. -6-
RAMBUS’S MOTION FOR RECONSIDERATION C 05-00334 RMW; C 05-02298 RMW; C 06-00244 RMW
Case 5:05-cv-00334-RMW
1 2
III.
Document 2066-2
Filed 08/19/2008
Page 10 of 10
CONCLUSION For the reasons set forth above, Rambus respectfully requests that the Court
3
construe “memory device,” as used in the asserted claims of the Farmwald/Horowitz patents, as
4
being restricted to a single chip.
5 DATED: August 19, 2008
MUNGER, TOLLES & OLSON LLP
6 SIDLEY AUSTIN LLP 7 McKOOL SMITH P.C. 8 9 By: 10 11
/s/ Peter A. Detre PETER A. DETRE
Attorneys for RAMBUS INC.
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 -7-
RAMBUS’S MOTION FOR RECONSIDERATION C 05-00334 RMW; C 05-02298 RMW; C 06-00244 RMW
