2 Ghz W-cdma Radio Transceiver

2 GHz W-CDMA Radio Transceiver by Cheung, Tze Chiu

Thesis submitted to the Faculty of the Virginia Polytechnic Institute and State University in partial fulfillment of the requirements of the degree of Master of Science in Electrical Engineering

APPROVED:

Dennis G. Sweeney, Chairman

Charles W. Bostian

Brian D. Woerner

December, 1998 Blacksburg, Virginia

Table of Contents

1.

2.

3.

Introduction................................................................................................................ 1 1.1

Motivation...................................................................................................... 1

1.2

Objective ........................................................................................................ 2

1.3

Outline of Thesis ............................................................................................ 2

System Overview ....................................................................................................... 4 2.1

Operating Band Structure............................................................................... 4

2.2

Code Division Multiple Access ..................................................................... 6

2.3

Data and Chip Rate ........................................................................................ 7

2.4

Channel Bandwidth........................................................................................ 7

2.5

Spreading and Modulation ............................................................................. 8

2.6

Transmit, Adjacent Channel and Spurious Power ......................................... 9

2.7

Receiver Sensitivity ..................................................................................... 12

2.8

Automatic Gain Control............................................................................... 12

2.9

Automatic Frequency Control...................................................................... 13

2.10

Receiver Selectivity and Spurious Response ............................................... 14

2.11

Diversity Receiver........................................................................................ 15

Radio Design............................................................................................................ 17 3.1

Transmitter ................................................................................................... 18 3.1.1

Block Diagram .............................................................................. 18

3.1.2

Technical Specifications ............................................................... 19

3.1.3

Design Approach and Analysis..................................................... 20

3.1.4

3.1.3.1

Peak-to-Average Factor ................................................. 20

3.1.3.2

Power Amplifier Requirement ....................................... 27

3.1.3.3

Receiver Desensing........................................................ 27

3.1.3.4

Transmit Power Control................................................. 29

Circuit Level Design ..................................................................... 29 3.1.4.1

Table of Contents

Digital-to-Analog Conversion Board............................. 29

iv

3.2

3.1.4.3

Transmit Power Control................................................. 35

3.1.4.4

Power Amplifier............................................................. 36

3.1.4.5

Duplexer – Transmitter Part........................................... 38

3.2.1

Block Diagram .............................................................................. 42

3.2.2

Technical Specifications ............................................................... 43

3.2.3

Design Approach and Analysis..................................................... 45 3.2.3.1

Receiver Noise Figure.................................................... 45

3.2.3.2

Heterodyne Architecture and Spurious Analysis ........... 47

3.2.3.3

Cascaded Receiver Chain Analysis................................ 56

3.2.3.4

Automatic Gain Control................................................. 63

Circuit Level Design ..................................................................... 65 3.2.4.1

Duplexer – Receiver Part ............................................... 65

3.2.4.2

Receiver Board............................................................... 65

3.2.4.3

Demodulator Board........................................................ 72

3.2.4.4

Analog-to-Digital Converter (ADC) Board ................... 73

3.2.4.5

Automatic Gain Control (AGC) Driver ......................... 73

3.2.4.6

Automatic Frequency Control (AFC) Board.................. 76

Synthesizer ................................................................................................... 78 3.3.1

Block Diagram .............................................................................. 79

3.3.2

Technical Specifications ............................................................... 80

3.3.3

Synthesizer Board ......................................................................... 80

3.3.4

4.

Modulator Board ............................................................ 32

Receiver........................................................................................................ 41

3.2.4

3.3

3.1.4.2

3.3.3.1

Design Modifications ..................................................... 80

3.3.3.2

Loop Filter ..................................................................... 85

Splitter Board ................................................................................ 87 3.3.4.1

RF Channel .................................................................... 87

3.3.4.2

IF Channel...................................................................... 88

Radio Performance................................................................................................... 90 4.1

Transmitter ................................................................................................... 90 4.1.1

Table of Contents

Transmit Power ............................................................................. 90 v

4.1.2 4.2

5.

Transmit Power Control................................................................ 94

Receiver........................................................................................................ 96 4.2.1

Receiver Noise Figure................................................................... 96

4.2.2

Automatic Gain Control (AGC) Performance .............................. 97

4.2.3

Receiver Desense .......................................................................... 99

4.2.4

Adjacent Channel Selectivity........................................................ 99

4.2.5

Intermodulation Selectivity......................................................... 100

4.2.6

Automatic Frequency Control (AFC) Characteristic .................. 102

Conclusions............................................................................................................ 103 5.1

Summary .................................................................................................... 103

5.2

Recommendations ...................................................................................... 103

Appendix A. Radio Specifications................................................................................. 105

Appendix B. Block Diagram.......................................................................................... 107

Appendix C. Schematics ................................................................................................ 108

Appendix D. Spurious Analysis..................................................................................... 114

Appendix E. PLL Programming Information ................................................................ 121

References ....................................................................................................................... 125 Vita ................................................................................................................................ 127

Table of Contents

vi

1. Introduction

1.1

Motivation

Wireless communications is going under explosive growth. Today, there are approximately 100 million mobile subscribers. The number of mobile users is expected to reach 1 billion by 2010 [1]. In Japan, this enormous growth of the mobile users is especially prominent. Currently, subscribers are increasing at a monthly rate of 0.8-1 million. The total number of mobile users was approximately 31.5 million at the end of March 1998 [2]. Because of the high growth rate, Japan has an aggressive plan for developing 3rd-generation mobile systems to solve the spectrum shortage of the current 2nd-gerneration communications systems - Personal Handyphone System (PHS) and Personal Digital Cellular (PDC). The main goal of the 3rd-generation cellular system is to offer seamless wideband services across a variety of environments, including 2 Mbps in an indoor environment, 384 kbps in a pedestrian environment and 144 kbps in a mobile environment [2]. The Japanese 3rd generation system employs wideband code division multiple access (WCDMA) technology. The International Telecommunications Union (ITU) is also considering W-CDMA technology for a global standard - IMT-2000. The ITU is an international standards body of the United Nations. The system approach is leading to a revolutionary solution instead of an evolutionary solution from the current IS-95 CDMA system. IS-95 was designed based on the needs of voice communications and limited data capabilities, but the 3rd-generation requirements include wideband services such as highspeed Internet access, high-quality image transmission and video conferencing [3]. The current IS-95 CDMA standard specifies 1.25MHz channel bandwidth and 1.2288Mchip/s chip rate. The relatively narrow bandwidth and low chip rate makes it impossible for IS95 to meet the data rate requirement of the 3rd-generation. While the cdma2000 system, which supports CDMA over wider bandwidths for capacity improvement and higher data rates, will maintain backward compatibility with existing IS-95 CDMA systems, the WCDMA system will use dual-mode terminals to retain the backward compatibility.

Introduction

1

NTT DoCoMo, Japan’s biggest cellular operator, intends to introduce the 3rd-generation mobile system based on W-CDMA [4]. According to NTT DoCoMo’s schedule, a system trial took in place in Tokyo by the end of 1997. The first indoor tests were scheduled to begin in April 1998, with outdoor tests commencing in October 1998 [4]. Texas Instruments is one of the participants in the experiments with this revolutionary technology. Texas Instruments approached CWT to participate in the experiments and to develop the W-CDMA radio.

1.2

Objective

Once the system is commercialized at the beginning of 2001 [2], the demand of mobile terminal equipment is expected to be huge. Mobile communications has become a demand-led industry. Short time-to-market is very critical to the success of a terminal product. A systematic design procedure of the radio portion of terminal equipment is important to shorten the product design cycle. In order to formulate a design procedure for this revolutionary system, a clear understanding of the system and signal characteristics is necessary to parameterize the radio design.

The primary goal of the research work is to build a radio transceiver that fully complies with the radio specifications of the W-CDMA system and to establish a systematic design procedure. The focus of this work is on the radio portion, while the baseband portion is handled by the sponsor, Texas Instruments. Appendix A is a summary of the radio specifications. Analysis and simulations have been performed to explain some of the requirements of the radio design.

1.3

Outline of Thesis

The presentation of this thesis is organized from the system level down to the circuit level. The outline is as follows: Chapter 2 gives an overview of the system. Chapter 3 discusses the design detail of the radio. Chapter 3 comprises three main sections. Each section presents a major sub-system of the radio. They are the transmitter, the receiver

Introduction

2

and the synthesizer. The block diagram of the sub-system is given at the beginning of the section. Following is a summary of the technical specification. The design approach and analysis are discussed next. Finally, the discussion is down to the circuit level of describing the part selection and circuit topologies. Chapter 4 presents the performance of the radio. Chapter 5 concludes the thesis and gives a recommendation for extending this work.

Introduction

3

2 System Overview

This chapter gives an overview of W-CDMA systems that is relevant to the radio design.

2.1

Operating Band Structure

The W-CDMA radio of this work operates in the 1920-1980MHz band for the uplink (from mobiles to base stations) and 2110-2170MHz band for the downlink (from base stations to mobiles). These are the main bands for IMT-2000 and are designated as Band A for the uplink and Band A′ for the downlink [2]. These two bands are in the 230MHz global spectrum identified by the ITU World Administrative Radio Conference (WARC92) [5] for a worldwide standard called the Future Public Land Mobile Telephone System (FPLMTS) – renamed International Mobile Telecommunication 2000 (IMT-2000) in mid-1995. The FPLMTS is a 3rd generation globally compatible digital mobile radio system that would unify the diverse systems such as paging, cordless, and cellular systems, as well as low earth orbit (LEO) satellites, into a common flexible radio infrastructure. Figure 1 shows the frequency plan of the 230MHz global spectrum in Japan [2]. 1893.5 1919.6 C

1885

PHS

A

MSS↑ B

1980 2010 2025

1920

A′

2110

MSS↓

2170

2200 MHz

MSS: Mobile satellite service PHS: Personal Handyphone System – a standard supports indoor and local loop applications in Japan (1)

A (1920-1980 MHz), A′ (2110-2170 MHz) – the radio operating band

(2)

B (2010-2025 MHz) – Time-division-duplex (TDD) system

(3)

C (1885-1895 MHz, 1918.1-1920 MHz) – PHS use

Figure 1.

The frequency plan of the 230MHz global spectrum for IMT-20000 in Japan.

System Overview

4

The W-CDMA is a frequency division duplex (FDD) system. FDD allows a simultaneous two-way communication by employing two separate frequency channels. The frequency separation between the transmit and receive channels is 190MHz. The lower band (A) carries information from the mobile terminals to the base stations. On the other hand, the upper band (A‘) carries information from the base stations to the mobile terminals. The traffic from the mobile terminals to the base stations is called the uplink, while the traffic from the base stations to the mobile terminals is called the downlink.

Both the A and the A‘ bands are 60MHz wide. Both of them are divided into twelve frequency channels. Each frequency channel is 5MHz wide. Two channels, which are 190MHz apart, are called a duplex pair. A duplex pair provides simultaneous two-way communication. Figure 2 shows the operating band structure for the mobile terminals. Tx - Lower Band 60MHz

Rx - Upper Band 60MHz 190MHz

1

2

3

10 11 12

1

2

3

10 11 12

fo

5MHz

Figure 2.

Single channel having center frequency fo

Operating band structure to mobile terminals.

The twelve duplex pairs permit frequency division multiple access (FDMA). FDMA means that a number of two-way communications can be conducted simultaneously by assigning each communication to a different duplex pair. This operating band structure provides for twelve channels in terms of FDMA. This is very low. However, the multiplexing power in W-CDMA is not from the FDMA. It is from the code division multiple access (CDMA). Fukasawa [6] showed that the 5MHz channel capacity of the W-CDMA is 82. It is 3.4 times the capacity of current analog cellular systems (AMPS).

System Overview

5

2.2

Code Division Multiple Access (CDMA)

W-CDMA is a direct sequence spread spectrum (DSSS) system. Code division multiple access (CDMA) is a unique trait of spread spectrum systems. The terminologies of CDMA and spread spectrum basically refer to the same type of systems. In cellular applications, CDMA is generally used to emphasize the multiple access nature of the systems.

The direct sequence spreading process multiplies an information stream with a high chip rate pseudo-noise (PN) code. Since the information stream is relatively low data rate as compared to the chip rate, the spectrum of the spread output is considerably wider than the original information stream. The PN code is the signature of the spread signal. This embedded signature allows despreading with a synchronized replica of the PN code at the receiving end.

W-CDMA systems spread the bandwidth of an information stream to a much wider bandwidth and lower the power spectral density (PSD) accordingly. As a result of PN codes, a spread signal has a noise-like quality. The transmit spread signal from an additional user causes a slight rise in the noise floor to the current users in the channel. The degradation of the performance of the receivers due to this additional power from the transmitter ultimately limits the system capacity. This is the most important characteristic of the W-CDMA system. Power becomes the common shared resource for users [7]. The interference power is shared between the mobile terminals in the cell and each terminal contributes to the interference. Radio resource management is to allocate power to each user such that the maximum interference is not exceeded. The system can easily add a user on the spectrum until the interference becomes intolerable. This is the real advantage of the W-CDMA. In cellular terms, frequency reuse is one. Everyone shares all the frequencies and the interference is uniformly spread over all the users. On the other hand, FDMA and TDMA systems have a well-defined number of users based on the available spectrum and time slots respectively. Therefore, the W-CDMA gives more flexibility on cell capacity management.

System Overview

6

Power management provisions and tolerance of co-channel interference in W-CDMA systems allow the use of the same frequency in adjacent cells. A frequency assignment plan is no longer needed. In FDMA and TDMA cellular systems, each cell only uses a part of the whole operating band in order to avoid adjacent channel interference. The number of available channels of a cell is inversely proportional to the cluster size. A cluster in cellular systems is a group of cells that collectively use the whole operating band. A typical cluster size is 7. Thus, the available channels of a cell are only a seventh of the total. On the other hand, all the cells can use the whole operating band in the WCDMA. W-CDMA can boost the system capacity dramatically.

2.3

Data and Chip Rate

The radio of this work is specified for 128Kbps data rate and 4.096Mcps chip rate. The full

W-CDMA

specification

allows

variable

data

rates

and

chip

rates

at

1.024/4.096/8.192/16.385Mcps [3]. Spreading involves the data and chip sequences. The data sequence is the information stream and the chip sequence is the spreading code. The information stream is a relatively low bit rate sequence, while the spreading code is a relatively high chip rate sequence. The ratio of the chip rate to the data rate defines the processing gain (PG) of the system.

 Rchip PG = 10 ⋅ log  Rdata

  

dB

(2.1)

The PG for the specified chip rate and data rate of the radio is 15dB.

2.4

Channel Bandwidth

As mentioned in Section 2.1, the channel bandwidth is 5MHz. The full W-CDMA specification allows the channel bandwidths of 1.25/5/10/20MHz [3]. The 5MHz bandwidth is the direct result of the choice of the chip rate and the pulse shaping filter. W-CDMA specifies a square root raised cosine pulse shaping filter with roll off factor of

System Overview

7

0.22. The use of a pulse shaping filter is to conserve the channel bandwidth. The square root raised cosine filter satisfies the Nyquist criterion such that the introduction of the pulse shaping does not cause intersymbol interference. Rectangular pulses without shaping requires the channel bandwidth to be double of the pulse rate. However, if rectangular pulses are shaped with the filter, the channel bandwidth is give by BWss = (1 + α ) ⋅ Rchip

(2.2)

where

α = 0.22

: is the roll-off factor of the square-root raised cosine filter.

The channel bandwidth is found to be 4.997MHz≈5MHz.

The choice of a wide channel bandwidth can achieve high data rate. For instance, the 5MHz bandwidth can support a data rate up to 384Kbps. The use of a wide channel bandwidth enables RAKE receivers to resolve more multipaths. This improves the receiver sensitivity or lowers the transmit power requirement for mobile terminals. Adachi and Sawahashi [8] demonstrated the decrease of the transmit power with increasing the spreading bandwidth on a field experiment in Tokyo. Thus the W-CDMA can accommodate more users on a frequency channel.

2.5

Spreading and Modulation

W-CDMA specifies a two-layered spreading structure. The 1st spreading code is a short code for channelization purposes. The code is derived from a Walsh/Hadamard function. The spreading code for the 2nd layer spreading is a long Gold code for randomization. The spreading process is not included in this work. It is performed in the baseband processor. A detail discussion can be found on [9]. The baseband processor sends the direct (I) and quadrature (Q) spread sequences in digital format to the radio. The radio uses quadrature phase shift keying (QPSK) technique to modulate the sequences on the carrier.

System Overview

8

2.6

Transmit, Adjacent Channel and Spurious Power

The transmitter is specified to have the maximum output power in the range from 29dBm to 33dBm. The output power is controllable over 70dB range - the minimum output power is from –41dBm to –37dBm. The power control step size is 1dB.

Transmitter power control (TPC) is essential to direct sequence spreading spectrum (DSSS) systems. It is required to combat the near-far problem. The near-far problem refers to a neighboring transmitter that can overpower a desired signal from a far transmitter. Without power control, interference will not be spread uniformly over all users. The near-far problem can degrade the system capacity tremendously.

W-CDMA provides TPC on both the uplink and the downlink. There are two types of the TPC: open-loop TPC and closed-loop TPC [10].

Open loop TPC is used when closed-loop TPC cannot be applied. For instance, a mobile terminal wants to access the system. Since the mobile terminal is not talking with the base station, it has to estimate the path loss of the channel by measuring the received power level of the perch channel from the base station. The perch channel provides the transmission level of the base station. The perch is a uni-directional channel from base stations to mobile terminals. Based on the measured result and the given transmission level, the mobile station can calculate the path loss and determine the transmit power.

Once the connection is established between the mobile station and base station, the closed-loop TPC is used. The closed-loop TPC is based on the signal-to-interference ratio (SIR). Figure 3 show an example of the TPC process configuration.

System Overview

9

Received Signal

Matched Filter

Rake Combiner

Viterbi Decoder

SIR Measurement

Frame Error Detector

Measured SIR Transmitter Power Up/Down Command

Inner Loop Control

Frame Error Rate Outer Loop Control

Target SIR

Figure 3.

An example of TPC process configuration.

The closed-loop TPC involves two sub-loops: the inner loop and the outer loop. The outer loop adjusts the target SIR based on the quality of the received signal. The inner loop measures the SIR of the received signal. If the measured SIR is higher than the target SIR, a bit called the TPC is set to “0”. This TPC bit commands the transmitter to lower the transmit power by 1dB. Whereas, the TPC is “1”, the transmitter has to increase the transmit power by 1dB.

W-CDMA specifies the power control cycle to be 0.625ms. The fast control cycle makes possible tracking rapid multipath fading. The fast TPC can always minimize the transmit power according to the traffic load. Thus, the mutual interference between users is minimized or the channel capacity is maximized. Moreover, keeping the transmit power low helps to conserve the battery power. The battery life is prolonged.

W-CDMA specifies 5MHz channel bandwidth and 4.997MHz spread signal bandwidth. There are almost zero guard bands between adjacent channels. This imposes a stringent requirement on the adjacent channel power. Table 1 lists spectral leakage specifications of the radio. Figure 4 shows the specification pictorially.

System Overview

10

Table 1.

The spectral leakage specification of the radio.

Adjacent Channel Leakage

Spurious Emission

-40dBc in 5MHz band

5MHz from the center

-60dBc in 5MHz band

10MHz from the center

-60dBc or less

All spurs other than adjacent channel leakage External CW interferer

Transmitter Intermodulation -60dBc or less

33dBm

2110

5MHz

2170 MHz

40dB 60dB Receive Band

fo

10MHz

Transmit Signal Spectrum

Figure 4.

The spectral leakage diagram.

The use of QPSK linear modulation raises a design conflict with the adjacent power requirement. QPSK signals are passed through the square root raised cosine filter to limit the signal bandwidth in 5MHz. The QPSK signals lose their constant envelope property after this filter operation. The peak-to-average factor of the filtered envelope of a QPSK signal is around 4.6dB on average.

Non-constant envelope signals must be amplified by linear amplifiers to prevent spectral regrowth. Because of the large peak-to-average factor of the QPSK modulated signal, the back off from the 1dB output compression point of the amplifier is large. The large back off causes inefficient power amplification or less battery life. The power handling capability of the amplifier has to be considerably greater than the required average power output.

System Overview

11

2.7

Receiver Sensitivity

W-CDMA employs pilot symbol-aided coherent detection to optimize receiver sensitivity. The pilot symbols associates in the both uplink and downlink as shown in Figure 5 [10].

Pilot

TPC

Q Data

Downlink I

Q

Pilot

TPC

Uplink Data I

Figure 5.

Multiplexing of pilot symbols.

The pilot symbols on the downlink are time multiplexed with the TPC command and the data; while the pilot symbols on the uplink are IQ multiplexed. The pilot symbols are used for channel estimation at the receivers. The estimation allows the coherent detection and automatic frequency control. Detection can achieve 10-3 BER at 6dB or less Eb/No on the traffic channel. The specified minimum input power is –113dBm at the receiver.

2.8

Automatic Gain Control (AGC)

1st-generation analog cellular systems used frequency modulation (FM). FM receivers use very high gain IF amplifiers with a limiter. The output to the detection circuits is fairly constant regardless the received signal strength. AGC is generally not found in analog cellular mobile units. However, this hard-limited non-linear amplification is not acceptable for quadrature phase shift keying (QPSK) modulated signals. In this case, an

System Overview

12

AGC circuit is essential to maintain a constant input to analog-to-digital converters (ADC). The AGC dynamic range is specified to be 80dB.

2.9

Automatic Frequency Control (AFC)

The channel estimation with pilot symbols gives a frequency estimation. The frequency estimation gives an input to the AFC so that the received signal can be converted to baseband precisely [11].

Let’s assume the received signal to be r (t − τ 0 ) = A(t − τ 0 ) ⋅ cos[(ω c + ∆ω )(t − τ 0 ) + Φ (t − τ 0 ) + θ 0 ]

(2.3)

where Φ(t )

: is the instantaneous phase.

τ 0 , ∆ω , θ 0

: are the unknown time delay, frequency error and phase offset respectively. They need to be estimated by the receiver.

The radio gets the estimated frequency error from the processor to drive the AFC so that the signal can be converted to baseband precisely. (2.3) can be resolved to the in-phase and quadrature components as I r (t ) = A(t − τ 0 ) ⋅ cos[∆ω ⋅ t − (ω c + ∆ω ) ⋅ τ 0 + Φ (t − τ 0 ) + θ 0 ]

(2.4)

Qr (t ) = A(t − τ 0 ) ⋅ sin[∆ω ⋅ t − (ω c + ∆ω ) ⋅ τ 0 + Φ (t − τ 0 ) + θ 0 ]

(2.5)

Figure 6 shows the rotating phasor of (2.4) and (2.5). R(t ) = I r (t ) + j ⋅ Qr (t ) = A(t − τ 0 ) ⋅ exp{ j ⋅ [∆ω ⋅ t − (ω c + ∆ω ) ⋅ τ 0 + Φ(t − τ 0 ) + θ 0 ]}

System Overview

(2.6)

13

Qr (t ) A(t − τ 0 )

∆ω ⋅ t − (ω c + ∆ω ) ⋅ τ 0 + Φ(t − τ 0 ) + θ 0

I r (t ) Figure 6.

Phasor of the received signal.

If the carrier can be tracked by the AFC such that ∆ω = 0 , the received signal will be a delayed version of the transmitted signal with a phase shift of − ω c ⋅ τ 0 + θ 0 . The received signal can be detected as the delay and phase estimations are found from the signal processing. However, if the AFC can’t track the signal for a zero frequency error, a constant-rate phase rotation of ∆ω ⋅ t keeps continuous moving of the signal constellation and detection is impossible. To accomplish the precise tracking, the AFC is specified to have very high frequency resolution at 0.03125ppm per step. The full tracking range is ±2ppm.

2.10

Receiver Selectivity and Spurious Response

To achieve the objective of maximizing the radio link performance, W-CDMA specifies the receiver selectivity and the spurious response. Table 2 lists the selectivity and spurious response to the radio. Figure 7 depicts the adjacent channel selectivity specification, while Figure 8 depicts the spurious response specification.

System Overview

14

Table 2.

The selectivity and spurious response specification of the radio.

Adjacent Channel Selectivity

33dB or more

@ 5MHz from the center

Intermodulation Response

60dB or more

@ 10 and 20MHz from the center

Spurious Response

60dB or more

@ 10MHz from the center

Adjacent Channel Interference 33dB desired signal center 5MHz

Figure 7.

The adjacent channel selectivity.

Intermodulation Pair

Spurious 60dB desired signal center 10MHz

10MHz 20MHz

Figure 8.

2.11

The spurious response.

Diversity Receiver

W-CDMA employs two receivers in the radio. One is the main receiver and the other is the diversity receiver. Providing 2-branch antenna diversity can significantly reduce the

System Overview

15

target Eo/No for a specific BER. Adachi and Sawahashi [8] have shown 3dB diversity gain for 10-3 BER on a field experiment in Tokyo.

The diversity receiver also facilitates the inter-frequency handover operation. W-CDMA employs hierarchical cell structures (HCSs) that overlay macrocells on top of smaller micro- or picocells. The HCSs boost system capacity and offer full coverage in urban environments. However, cells of different cell layers will operate on different frequencies as shown in Figure 9 [6]. This requires inter-frequency handover ability in the mobile terminals.

Macrocell

Microcell

Microcell Macrocell

Macrocell

f2 f1

f1 Inter-frequency handover

Figure 9.

Inter-frequency handover in HCS scenario.

In order to perform the seamless inter-frequency handover, the mobile terminal has to carry out a cell search on frequency channels different from the current frequency channel with no interruption to the current data flow. One of the receivers temporarily branches from diversity reception to perform cell search until the handover is completed.

System Overview

16

3.

Radio Design

The radio is the radio front-end of a mobile terminal. The radio consists of three major sub-systems: the transmitter, the receiver and the synthesizer. The radio has two identical receivers for the antenna diversity purposes. Additionally, the power control (PC), automatic frequency control (AFC) and automatic gain control (AGC) sub-circuits are essential for the W-CDMA system objectives. The digital-to-analog converters (DAC) and the analog-to-digital converters (ADC) are used for the interfaces between the radio and the baseband processor. Appendix B is a full block diagram of the radio.

The discussion in this chapter includes three major sections. Each section describes one of the sub-systems. The beginning of each section is the block diagram of the sub-system. Referring to the block diagram, the technical specification, the design approach and analysis, and the circuit implementation are presented.

Radio Design

17

3.1

Transmitter

The transmitter supports the uplink of the W-CDMA system. It provides a digital interface for the baseband processor. The baseband processor sends the spread baseband signal through the digital interface to the transmitter. The transmitter modulates the baseband signals on a radio frequency (RF) carrier. The modulated RF signal is then amplified, filtered and transmitted to the base station through the air link. To combat the near-far problem, the transmitter operates in conjunction with a transmit power control (TPC) to maintain the transmit power at an appropriate level. The control determines the power level based on the digital command from the baseband processor. Figure 10 is a block diagram of the transmitter.

3.1.1

Block Diagram

DAC

LPF

Local oscillator from Synthesizer

+45°

ATT

BPF

AMP

DAC

LPF

DAC

TPC

DAC - Digital-to-Analog Converter LPF - Baseband Low Pass Filter ATT - Attenuator AMP - Amplifier BPF - RF Bandpass Filter TPC - Transmit Power Control PA - Power Amplifier DUP-Tx - RF Duplexer (Transmitter Part)

Figure 10.

ATT

-45°

PA1

PA2 DUP-Tx

Transmitter block diagram.

Radio Design - Transmitter

18

3.1.2

Technical Specifications

The key specification for the transmitter is to deliver transmit power at 1.6 W +20%, 50% over the transmitting band (1920 – 1980 MHz). A digital command from the baseband processor can control the transmit power over a 70dB range. The digital command is 7-bits long. The command code is a binary number between 0000000B and 1000110B (or 0 to 70 decimal). The code 0000000B produces the maximum power output, while the code 1000110B produces 70dB less than the maximum output. The power control cycle time is 0.625ms.

The data rate is 128Kbps. The data sequence is spread with the spreading codes at 4.096Mcps chip rate. The modulation type is QPSK. The baseband processor sends the direct (I) and quadrature (Q) baseband signals to the transmitter in two separate channels. The baseband processor samples the baseband signals at 32.768Msps. The sample rate is eight times the chip rate. The signals are sent in 8-bit digital format. The transmitter digital-to-analog converters (DAC) reconstruct the analog signals and these signals are filtered by 0.22 roll-off, square root raised cosine (RRC) filter. The resulting analog signals are applied to the transmitter modulator.

As mentioned in Section 2.6 of the system overview, the zero guard bands between adjacent channels of the W-CDMA systems imposes a stringent requirement on the adjacent channel power. The adjacent channel power is measured with modulated signals. The adjacent channel power of the output spectrum is 40dBc less than the inband output power. The inband power is the total power in a 4.096MHz bandwidth about the carrier frequency. The adjacent channel power is the total power in the 4.096MHz bandwidth about the frequency that is ±5MHz away from the carrier frequency. The next adjacent channel power is the total power in the 4.096MHz bandwidth about the frequency that is ±10MHz away from the carrier frequency. The next adjacent channel power is 60dBc less than the inband power.

Radio Design - Transmitter

19

The spurious and intermodulation emission is measured with a continuous wave (CW). The emission should be 60dBc less than the CW carrier.

The full specifications of the transmitter are listed in Appendix A.

3.1.3

3.1.3.1

Design Approach and Analysis

Peak-to-Average Factor

As mentioned the system overview, a QPSK signal after pulse shaping will lose its constant envelope property. Non-linear power amplification of a non-constant envelope signal causes spectral regrowth. Understanding the peak-to-average factor of the QPSK signal is important in selecting the power amplifiers to avoid non-linear amplification.

A simulation was performed to find the peak-to-average factor based on the model shown in Figure 11. IQPSK

IS

QPSK I and Q Generator

Pulse Shaping Filter Random Data Generator

Signal Envelope

I s2 + Q s2 QQPSK Pulse Shaping Filter QS

Figure 11.

Simulation model for QPSK peak-to-average factor.

The model in Figure 11 is hypothetical. It does not include the W-CDMA spreading process but a random data generator was used to approximate the PN sequence. The QPSK modulation scheme is defined in Table 3 [12].

Radio Design - Transmitter

20

Table 3.

The QPSK modulation scheme.

Two Consecutive Bits 00 01 10 11

Signal Phase 225° 135° 315° 45°

The pulse shaping filters are 0.22 roll-off, square root raised cosine filters. The filter outputs are used to evaluate the signal envelope. The model is based on the complex baseband envelope which avoids the necessity of simulating the high frequency carrier.

QPSK

QPSK is a bandwidth efficient modulation scheme. As compared to the BPSK modulation scheme, QPSK gives the same BER performance but carries twice the data rate in the same bandwidth. The implementation of modulation and demodulation is simple, and, therefore, QPSK is very attractive for use in wireless communications.

The phase of a QPSK signal can take one of four possible values. The four values are equally spaced. They are practically chosen to be 45°, 135°, 225° and 315°. The QPSK can be mathematically represented by [13] S QPSK (t ) = A ⋅ cos[2πf c ⋅ t + θ i (t )]

(3.1.1)

where 0 ≤ t ≤ Ts

: Ts is the symbol duration.

i = 1, 2, 3, 4.

θ1 =

3π 5π 7π π , θ2 = , θ3 = , θ4 = . 4 4 4 4

A

: signal amplitude.

fc

: carrier frequency.

Radio Design - Transmitter

21

For a symbol interval, (3.1.1) can be written as S QPSK (t ) = A ⋅ cos[θ i (t )]⋅ cos(2πf c ⋅ t ) − A ⋅ sin[θ i (t )]⋅ sin( 2πf c ⋅ t )

(3.1.2)

The direct (I) and quadrature (Q) components of the signal are defined as I QPSK (t ) = A ⋅ cos[θ i (t )]

(3.1.3)

QQPSK (t ) = A ⋅ sin[θ i (t )]

(3.1.4)

The I and Q components are baseband signals that ease the simulation.

Square Root Raised Cosine Filter

The pulse shaping filter is a square root raised cosine filter. The pulse shaping reduces the intersymbol effects and the spectral bandwidth of baseband signals. The roll-factor of the filter is 0.22. The transfer function of the filter in frequency domain is given by [14]

   H RRC ( f ) =    

0≤ f ≤

1  πTs 1  1 + cos  2   α

 1 − α    f −   2Ts   

0

1−α 2Ts

1−α 1+α < f ≤ 2Ts 2Ts f >

(3.1.5)

1+α 2Ts

where

α

: is the roll-off factor.

Radio Design - Transmitter

22

Figure 12 illustrates the ideal spectral characteristic of the square root raised cosine filter with a 0.22 roll-off factor. The x-axis is normalized to the symbol rate. As shown in the figure, the filter response is absolute zero after 0.61/Ts . Spectral Characteristic of Square Root Raised Cosine Filter with a 0.22 Roll-Off Frequency Response of Square Root Raised Cosine Filter at 0.22 Roll-off

1

Magnitude -|HRRC(f)| Magnitude - |Hrrc(f)|

0.8

0.6

0.4

0.2

0 -1

Figure 12.

-0.8

-0.6 -0.4 -0.2 0 0.2 0.4 0.6 Frequency tothe thesymbol symbolrate) rate) Frequency (normalized (normalized to

0.8

1

Spectral Characteristic of square root raised cosine filter with a 0.22 rolloff.

The number of points used to sample the spectrum is 1024. An Inverse Fourier transform (IFT) is used to obtain the time-domain impulse response of the filter. However, the resulting filter is non-causal. The impulse response is an infinite time waveform about the time zero. This impulse response cannot be implemented practically. Thus, the impulse response is delayed by four symbol intervals. The first eight symbol intervals are considered and the rest are truncated. Figure 13 shows the delayed and truncated impulse response of the filter.

Radio Design - Transmitter

23

Impulse Response of Square Root Raised Cosine Filter with a 0.22 Roll-Off Impulse Response of Square Root Raised Cosine Filter 0.07 0.06 0.05

hRRC(t) Magnitude

0.04 0.03 0.02 0.01 0 -0.01 -0.02

Figure 13.

0

1

2

3

4 5 6 Time, Tb Time (normalized to the symbol period)

7

8

Delayed and truncated impulse response of the square root raised cosine filter with a 0.22 roll-off.

Pulse Shaped I and Q signals

Pulse shaping is done by passing the I and Q signals through the filters individually. Mathematically, it is equivalent to convolve the signals with the impulse response. I s (t ) = I QPSK (t ) ⊗ h RRC (t )

(3.1.6)

Q s (t ) = QQPSK (t ) ⊗ h RRC (t )

(3.1.7)

Radio Design - Transmitter

24

Simulation

A simulation was used to generate 512 bits of random data. Two bits form a QPSK symbol. The QPSK symbols generate the I and Q symbols. Each symbol is sampled for 16 samples. Convolution is performed on the I and Q sampled sequences with the filter impulse response. Figure 14 shows a 50-sample segment of the I and Q signals before and after pulse shaping. Direct Signal (I-Channel) Time Waveform

Direct Signal (I-Channel) Time Waveform 1.5 Original Input Shaped Output 1

Amplitude, Amplitude, voV lts

0.5

0

-0.5

-1

-1.5 50

55

60

65

70

75

80

85

90

95

100

Quadrature Signal (Q-Channel) Time Waveform Direct Signal (Q-Channel) Time Waveform 1.5 Original Input Shaped Output 1

Amplitude, V Amplitude, volts

0.5

0

-0.5

-1

-1.5 50

55

60

65

70 75 80 Symbol Period, Ts

85

90

95

100

Symbol Periods, Ts

Figure 14.

A 50-sample segment of the I and Q signals before and after shaping.

Radio Design - Transmitter

25

The complex envelope of the pulse shaped QPSK signals for the 50-sample segment is shown in Figure 15. Signal Envelope Time Waveform

Signal Envelope Time Waveforms 1.5

0.5

Magnitude, volts

Amplitude, V

1

0

-0.5

-1

-1.5 50

55

60

65

70

75

80

85

90

95

100

Symbol Periods, Ts

Figure 15.

The shaped signal envelope of the 50-sample segment.

Referring to the Figure 14, the original I and Q signals are digital waveforms and the amplitude is -0.707V or 0.707V. This results in unity envelope amplitude. Figure 15 shows that the envelope of the shaped signal is no longer constant. The peak-to-average factor can be found from the simulated samples of the signal envelope waveform by (3.1.8).

F pk / avg =

max( I s2 (k ) + Q s2 (k ) ) 1 N ⋅ ∑ I s2 (k ) + Q s2 (k ) N k =1

(3.1.8)

where N

: total number of samples

k

: sample index from 1 to N

Evaluating (3.1.8) results in a peak-to-average factor of approximately 4.6dB.

Radio Design - Transmitter

26

3.1.3.2

Power Amplifier Requirement

According to the specifications, the average output power of the transmitter should be 1.6W within a tolerance of -50% to +20% at the antenna port. The stringent adjacent channel power requirement and the non-constant envelope QPSK signal prevent the use of high-efficiency non-linear amplifiers. However, the use of linear power amplifiers for high output power results in much higher power drain and implementation cost. To compromise the shortcomings of linear amplification, we set the target output power of the transmitter at 1W or 30dBm.

As shown in the block diagram in Section 3.1, there is a duplexer filter before the power is delivered to the antenna. The insertion loss imposed by the filter is unavoidable. This insertion is estimated to be 1.5dB. Thus, the power amplifier has to deliver 31.5dBm average power. The power amplifier should not introduce non-linear distortion at the peak of the QPSK signal that has a 4.6dB peak-to-average factor. Thus, the power handling capability of the amplifier should be 36dBm or more. Power amplification of the modulator output level to 30dBm is difficult to achieve in one stage. Two-stage power amplifiers were used.

3.1.3.3

Receiver Desensing

The power amplification not only boosts the power level of the desired transmit signal but also raises the noise floor of the spectrum. The rise of the spectrum noise floor can include the receiving band (2110-2170MHz) which is 190MHz higher than the transmitting band. However, the transmitter and the receiver share an antenna through the duplexer. The duplexer is a three-port filter. The three ports accommodate the transmitter, the receiver and the antenna simultaneously. The use of the duplexer saves an antenna. On the other hand, it introduces a physical path between the transmitter and the receiver. If the power in the receiving band due to the transmitter is not properly suppressed, turning on the transmitter will degrade the receiver sensitivity. This phenomena is called receiver desensing.

Radio Design - Transmitter

27

A power budget study is done to ensure no receiver desense. Figure 16 depicts the specified transmit power spectrum.

30dBm 2110 5MHz

40dB 60dB

fo

2170 MHz

Receive Band

10MHz

Target Transmit Power Spectrum

83dB

Less than –113dBm

Filter Suppression

Figure 16.

The specified transmit power spectrum.

The transmit power spectrum specifies for a 30dBm transmit carrier. The adjacent channel power and out-band suppressions are 40dBc and 60dBc respectively. The transmit power spectrum has 60dB suppression in the receiving band. The noise floor in the receiving band due to the transmitter is –30dBm (i.e. 30dBm – 60dB). This noise floor is much greater than the specified –113dBm receiver sensitivity. The transmitter can cause serious receiver desense.

Filtering the transmit power spectrum is necessary to drive down the noise floor in the receiving band by 83dB or more. The duplexer and the RF bandpass filter (BPF) in the transmitter are the devices used to provide the suppression. They will be discussed in the circuit level design section.

Radio Design - Transmitter

28

3.1.3.4

Transmit Power Control (TPC)

The transmitter should provide 70dB transmit power control range. Specifying the target output power as 30dBm, the range of the transmit output power is from –40dBm to 30dBm. In order to achieve the power control, RF attenuators are used to adjust the power amplifier drive level. It is difficult to use one attenuator to provide the 70dB control range. The board feed-through can limit the maximum isolation between two nodes on the printed circuit board. If the intended attenuation of an attenuator is greater than the board feed-through, the attenuation becomes board limited rather than device limited. The attenuation of the attenuator beyond the board limit becomes unpredictable. Two attenuators were employed in the transmitter chain to ensure that the attenuation is device limited.

3.1.4

Circuit Level Design

Following the flow of the signal as shown in the block diagram in Section 3.1.1, the discussion of this section proceeds from the digital interface to the duplexer. Detailed schematics are in Appendices C-1 and C-2. The discussion of the circuits refers to the schematics for the component designators. The hardware implementation of the transmitter comprises five assemblies. They are the digital-to-analog board, the modulator board, the power control, the power amplifier and the duplexer. Each assembly is discussed in following sub-section.

3.1.4.1

Digital-to-Analog Conversion (DAC) Board

The DAC board provides the interface between the baseband processor and the transmitter. It accepts the I and Q baseband signals in 8-bit digital format from the baseband processor and outputs the I and Q signals in analog form to the modulator. Figure 17 is the DAC block diagram. The full schematic is in Appendix C-1.

Radio Design - Transmitter

29

Direct (I) Channel DAC AMP

AMP

DAC

Quadrature (Q) Channel

to modulator 0.5Vpk

LPF AMP

Figure 17.

0.5Vpk

LPF

AMP

AMP - operational amplifier LPF - Low Pass Filter

Block diagram of the DAC board.

AD9708 DAC

The AD9708 is a 8-bit digital-to-analog converter from Analog Devices. There are two AD9708’s (Appendix C-1: U1, U3) on the board. Each device corresponds to one (I or Q) baseband channel. They convert the digital baseband signals from the baseband processor to analog signals. The devices are capable of 100Msps but actually operate at 32.765Msps. The devices are set for a full range differential output at 0.5V peak.

AD8072 Operational Amplifier

The outputs of the DACs are connected to the Analog Devices AD8075 operational amplifiers. There are two AD8075’s (Appendix C-1: U2, U4) on the board. Each device corresponds to one baseband channel. Each AD8075 package contains two operational amplifiers. One of the amplifiers buffers the DAC from the baseband low pass filter (LPF) and provides a voltage gain of two. The other amplifier buffers the LPF output from the modulator. The voltage gain of this amplifier is adjusted so that the full-scale output to the modulator is 0.5V peak.

Radio Design - Transmitter

30

Baseband Low Pass Filter

The baseband low pass filters are from Soshin. They are 0.22 roll-off square root raised cosine filters. There are two filters (Appendix C-1: F1, F2) on the board. Each filter corresponds to one baseband channel. They are pulse shaping and anti-aliasing filters. Pulse shaping is performed to limit the baseband signal bandwidth. The DAC outputs are composed of the baseband spectrum and the replicas of the baseband spectrum at every integer multiple of the 32.768MHz sampling frequency. The filters remove all the replicas to prevent aliasing. The measured frequency response of the filter is shown in Figure 18. Frequency Response of Baseband Square Root Raised Cosine Filter 0

-5

-10

-15

-20

-25

-30

-35

-40 0

500000

1000000

1500000

2000000

2500000

3000000

Frequency in Hz

Figure 18.

Frequency response of the Soshin baseband low pass filter.

The filter starts to roll-off at 1.6MHz and the absolute cut-off is at 2.6MHz. Comparing the theoretical response of the filter given in Figure 12 of Section 3.1.3.1 that the actual roll-off starts at 1.64MHz and the absolute cut-off is 2.46MHz. There are small

Radio Design - Transmitter

31

differences between the theoretical values and the measured values. These are the measurement errors. The measurement error at the absolute cut-off is larger because the signal to be measured at the absolute cut-off is small. The measurement accuracy is more vulnerable to the noise influence in the system.

3.1.4.2

Modulator Board

The modulator board performs the modulation and power control functions. Figure 19 is the block diagram. The full schematic is in Appendix C-2.

I-Channel 0.5Vpk +45°

RF Carrier -1.5dBm

ATT

ATT

-45°

-13dBm

AMP Power Control Voltage

Q-Channel 0.5Vpk

Figure 19.

BPF

Block diagram of the modulator board.

RF2422 Modulator

The modulator chip (Appendix C-2: U4) is a RFMD RF2422. It modulates the baseband signals on the RF carrier (1.92GHz – 1.98GHz). The RF carrier level is set at –1.5dBm, while the both I and Q baseband signal levels are set at 0.5V peak. This baseband input was set to maintain low adjacent channel power. The modulated output has 50dB adjacent channel power suppression that gives 10dB margin for the subsequent power amplifier with respect to the –40dBc specification.

Radio Design - Transmitter

32

AT-108 Attenuator

There are two M/A COM AT-108 attenuators on the modulator board. One (Appendix C2: U2) is at the modulator output and the other (Appendix C-2: U1) is at the output of an amplifier. The attenuator has 40dB attenuation range but the design makes use of a 35dB range to meet the 70dB control range requirement. The attenuation is determined by a control voltage from the transmit power control. The control voltage can run between 0 to 5V. A 5V voltage gives a minimum attenuation of 3.5dB which is the insertion loss of the attenuator. As the voltage decreases, the attenuation increases till the total attenuation is 43.5dB (the 40dB attenuation plus the 3.5dB insertion loss). For the 35dB attenuation range, the minimum control voltage is set at approximately 0.5V.

Amplifier

A Mini-Circuits ERA-5 monolithic amplifier (Appendix C-2: U3) is used as a gain block to compensate for the miscellaneous losses in the circuit, such as the insertion losses of the attenuator and the filter. The gain of this amplifier is 20dB. This amplifier has 50Ω standard input and output ports. It is easy to use and stable. The bias circuit is simple as shown in Figure 20 [15].

V cc

Cs

R b ia s

Ibias

L b ia s

IN

OUT

Vd

Cc

Cc

ERA

Figure 20.

Bias Configuration for ERA amplifiers.

Radio Design - Transmitter

33

The RF choke should be chosen such that its reactance is at least 500Ω. Based on this criterion, a 39nH choke is used.

The ERA-amplifiers are biased with a supply voltage (Vcc ) higher than the device voltage (Vd ) for stable performance. The higher supply voltage allows larger bias resistances ( Rbias ) and hence the variation of the bias conditions against temperature is reduced [15]. However, a large voltage difference is not favorable to the use of chip resistors because more voltage difference causes more power dissipation in the bias resistor. To allow the use of chip resistors, the 6V supply is chosen. The bias resistance is calculated (3.1.9) based on the bias parameters of the amplifiers from the data sheets.

Rbias =

(Vcc − Vd ) I bias

(3.1.9)

RF Bandpass Filter (BPF)

This is a dielectric filter (Appendix C-2: U7) from Soshin. Its passband band covers the transmit band with a 2.5dB insertion loss. Its out-band rejection is 30dB. It removes the spectral impurity of the signals. As mentioned in Section 3.1.3.3, there is a need for 83dB power suppression in the receiving band. This BPF produces 30dB of the suppression.

Resistive Pad There are two π-type resistive pads. Resistance values for π-type resistive attenuator is given in [16]. One (Appendix C-2: R11, R13, R16) is at the output of the modulator chip and the other (Appendix C-2: R70, R71, R72) is at the output of the RF BPF. The use of the pads improve the stability of the PA driver. They set the output level of the modulator at –13dBm. The –13dBm output level prevents the subsequent power amplifier from operating in saturation to ensure good adjacent channel power suppression.

Radio Design - Transmitter

34

3.1.4.3

Transmit Power Control (TPC)

The TPC resides on the automatic frequency control (AFC) board that will be discussed in the receiver section. The control includes an ADC and a level shifting circuit as shown in the block diagram in Figure 21. The schematic is in Appendix C-5. DAC

Figure 21.

TPC

Analog Voltage Output to Modulator Board

Block diagram of the power control.

The TPC accepts a 7-bit digital command from the baseband processor and provides a scaled analog voltage to drive the attenuator on the modulator board. The control voltage is connected to the two attenuators in parallel. The required attenuation is evenly distributed between the two attenuators. The command code is between 0000000B and 1000110B (or 0 to 70 decimal). The analog voltage output is from 5V to 0.5V. The code 0000000B produces 5V analog voltage output, while the code 1000110B produces 0.5V analog output.

AD557 DAC

The AD557 (Appendix C-5: U5) is a 8-bit digital-to-analog converter (DAC) from Analog Devices. It is the interface between the baseband processor and the TPC. The DAC has one bit more than the command length. In order to fully utilize the output range of the DAC, the command digits are tied to the most significant 7-bits of the DAC and the least significant bit is held high. Thus, the command is effectively multiplied by a factor of 2. Table 4 lists the input-output relationship of the DAC.

Table 4.

The input-output relationship of the DAC.

Output Power 30dBm maximum -40dBm minimum

Radio Design - Transmitter

Command 0000000 1000110

AD557 DAC out (V) 0.01 1.41

35

The 10mV residual voltage is a result of the least significant bit being tied high. The maximum output settling time of the DAC is 1.5µs so that the DAC easily supports the 0.625ms power control cycle time.

Level Shifting Circuit

The level shifting circuit is built with a LM6132 (Appendix C-5: U10) chip from National Semiconductor. The device contains two operational amplifiers. The two amplifiers form a two-stage level shifting circuit. The 1st stage is a voltage follower (Appendix C-5: U10A) required to buffer the DAC output. The 2nd stage is an inverting amplifier (Appendix C-5: U10B) needed to produce the phase inversion and the level shifting as shown in Table 5.

Table 5.

The input-output relationship of the level shifting circuit.

Output Power

Analog in from DAC (V)

Analog out (V)

30dBm maximum

0.01

5

-40dBm minimum

1.41

0.5

The exact level shifting is not well defined in practice because of the variation of the RF attenuation. Two variable resistors (VR) are used to provide the adjustment of the level shifting so that the variation can be compensated. One VR (Appendix C-5: R19) is used to shift the analog output up or down. The other VR (Appendix C-5: R18) is used to set the slope of the input-output relationship. The two adjustments provide the flexibility to set the maximum and minimum of the analog output.

3.1.4.4

Power Amplifier

The power amplifier boosts the –13dBm transmit signal from the modulator board to 31.5dBm. The output should have 40dBc or more adjacent channel power suppression.

Radio Design - Transmitter

36

The required gain of the amplifier is 44.5dB. As mentioned in Section 3.1.3.2, the power handling capability of the amplifier should be 36dBm to address the 4.6dB peak-toaverage factor of QPSK signals.

The power amplifier is a two-stage implementation for the high gain and high power requirement. Figure 22 is the block diagram.

-13dBm from modulator board

31.5dBm to duplexer Celeritek CCS1933

Figure 22.

Celeritek CFH2162-P3

Two-stage power amplifier.

Both stages are built with Celeritek devices. The 1st stage is the CCS1933 evaluation board from Celeritek. The first trial of the power amplifier implementation only utilized the CCS1933. However, the adjacent channel power suppression was unsatisfactory because the CCS1933’s power handling capability is 33dBm (3dB below the requirement). To address this problem, a 2nd stage is to be added after the CCS1933. CFH2162-P3 was chosen for this stage because it has 36dBm power handling capability. The 1st stage of the CCS1933 evaluation board produces 35dB gain and boosts the transmit power to 22dBm. Experiments reveal that the adjacent channel power suppression at the 22dBm power output is 41dBc.

The CCS1933 board consists of a driver amplifier (CMM1301) and a matched power amplifier (CFK2162-P3). Both of them operate from a 5Vdc supply. The CMM1301 drive amplifier is biased for 150mA drain current with a negative gate voltage. The CFK2162-P3 power amplifier is matched on board for 50Ω. It is biased for 1.2A drain current with another negative gate voltage. Both the negative gate voltages are derived from a –5Vdc supply through resistive potential dividers. The potential dividers are built

Radio Design - Transmitter

37

with multi-turn potentiometers to facilitate a precise bias adjustment. To prevent damage to the two amplifiers, the negative bias voltages must be applied to the amplifiers before the 5Vdc drain supply. The 2nd stage being considered is the Celeritek CFH2162-P3 power amplifier. The 1dB output compression point of the amplifier is 36dBm. This meets the required power handling capability of 36dBm. The input to this amplifier is around 22dBm and the amplifier delivers 31.5dBm transmit power. The 31.5dBm output power is 4.5dB below the 1dB output compression point so that linear operation of the amplifier will contribute insignificant adjacent channel power. Thus the specified 40dBc adjacent channel power suppression can be achieved.

3.1.4.5

Duplexer – Transmitter part

The duplexer was designed and built by Dr. Sweeney. It is a three-port filter device. It includes a transmitting bandpass filter and a receiving bandpass filter. The use of the duplexer allows the radio to simultaneously transmit and receiver on a single antenna. This saves the cost of a separate antenna and eases the system construction. Figure 23 depicts the physical layout of the duplexer. Antenna Port

1920MHz

1980MHz

Transmitter Port

Figure 23.

2110MHz

2170MHz

Receiver Port

Physical layout of the duplexer.

Radio Design - Transmitter

38

The output of the power amplifier is connected to the transmitter port of the duplexer. The insertion loss of the duplexer in the transmitting band is 1.5dB. Thus the available transmitter power at the antenna is 30dBm. As mentioned in Section 3.1.3.3, the use of the duplexer may cause the receiver desense if the suppression of the noise at the receiving band is not adequate. The transmitting bandpass filter of the duplexer is designed to have a notch at the receiving band. The notch gives 70dB rejection to the receiving band. This 70dB rejection and the 30dB rejection from the RF BPF makes up 100dB receiving band rejection that is higher than the required 83dB rejection. Thus the receiver desense problem is well addressed. Figure 24 shows the simulated characteristics of the duplexer.

TI Duplexer Characteristics

Tx Filter

Rx Filter

0

0 -2

-24

-4 -6

-48

-72

-8

Rx Band Rejection ≅76dB

Tx Band Rejection ≅76dB

-10 -12 -14

-96

-16 -18

-120 1.90

-20 1.95

2.00

2.05

2.10

2.15

2.20

Frequency (GHz) Rx - S21

Figure 24.

Tx - S31

Return Loss - S11

Duplexer Characteristics.

Radio Design - Transmitter

39

The receiving filter response curve (Rx-S21) shows that the transmit power rejection is approximately 76dB. The transmitting bandpass filter also provides approximately 76dB rejection to the receiving band as shown in the transmitting filter response curve (TxS31). The return losses of the filter in the receiving band and the transmitting band are both approximately 13dB as shown the return loss curve (Return Loss–S11).

The measured performance of the duplexer is tabulated in Table 6. The measured data match the simulated data well.

Table 6.

Measured performance of the duplexer.

Transmitting Band

Receiving Band

Insertion Loss (dB)

1.8

1.0

1dB Bandwidth (MHz)

71.3

66.3

3dB Bandwidth (MHz)

76.3

73.8

Receiving Band Rejection (dB) 2110 MHz

74

2140 MHz

71

2170 MHz

72

Transmitting Band Rejection (dB)

Radio Design - Transmitter

1920 MHz

74

1950 MHz

73

1980 MHz

74

40

3.2

Receiver

The receiver supports the downlink of the W-CDMA system. It receives the radio frequency signal from a distant base station. The front-end of the receiver processes the radio frequency (RF) and intermediate frequency (IF) signals. The demodulator of the receiver recovers the baseband signals from the IF signals. The last stage of the receiver consists of analog-to-digital converters (ADC). These converters are the interface between the receiver and the baseband processor. The converters digitize the baseband signals and provide the digital outputs to the baseband processor.

The receiver operates in conjunction with the automatic gain control (AGC) and the automatic frequency control (AFC). The AGC improves the dynamic range of the receiver by maintaining a constant signal level at the input of the ADCs. The AFC improves the receiver sensitivity by producing precise baseband demodulation.

There are two identical receivers in the radio. One of the receivers shares the antenna with the transmitter through the duplexer and is called the main receiver. The other receiver has its own diversity antenna and is called the diversity receiver. The two receivers provide an antenna diversity gain to improve the reception performance and facilitate the inter-frequency handover.

Figure 25 in the following section is the block diagram of the receiver. Only the main receiver is shown but the block diagram applies to the diversity receiver as well. The main and diversity receivers are identical.

Radio Design – Receiver

41

3.2.1

Block Diagram

DUP-Rx

LO 2

LO 1 LNA

BPF MIX 2

AMP 2

BPF

IF 1

AMP 1

MIX 1

ATT

RF

BPF AMP 3

ADC

IF 2

AMP 4 DEMOD

LPF BB AMP +45°

DAC

AFC

AGC AMP

÷2 -45° BB AMP

ADC

LPF

DAC

AGC

DUP-Rx - RF Duplexer (Receiver Part) LNA - Low Noise Amplifier ATT - Attenuator BPF - Bandpass Filter RF - Radio Frequency MIX - Mixer LO - Local Oscillation IF - Intermediate Frequency

Figure 25.

AMP - Amplifier AGC - Automatic Gain Control DEMOD - Demodulator BB - Baseband LPF - Low Pass Filter DAC - Digital-to-Analog Converter ADC - Analog-to-Digital Converter AFC - Automatic Frequency Control

Receiver block diagram (Only the main receiver is shown in the diagram. The main and diversity receivers are identical.)

Radio Design – Receiver

42

3.2.2

Technical Specifications

The key specification for the receiver is the reception sensitivity. The receiver produces 10-3 bit-error-rate (BER) at –113dBm or less input power level on the traffic channel. This received power level produces 6dB or greater Eb/No for the baseband processor to perform the detection. The traffic channel throughput is 128Kbps. The operating band of the receiver is 2110-2170MHz. The dynamic range of the receiver is 80dB. This means that the receiver can receive a signal from –113dBm to –33dBm. The AGC adjusts the gain of the receiver chain to maintain a constant signal level at the ADC inputs. The baseband processor provides the control command for the AGC. This digital command is 7-bit long. The command code is a binary number between 0000000B and 1010000B (or 0 to 80 in decimal). The code 0000000B produces the maximum gain of the receiver chain, while the code 1010000B produces a gain of 80dB less than the maximum.

The received signal is a QPSK modulated direct sequence spread spectrum signal. The bandwidth of the signal is 5MHz. The carrier frequency of the signal is in the receiving band (2110-2170MHz) which is 190MHz higher than the transmitting band. The receiver uses a double-conversion superheterodyne architecture. The 1st downconversion converts the received RF signal to a 190MHz IF. The 2nd down-conversion converts the 190MHz IF to a 70MHz IF. A QPSK demodulator recovers the baseband I and Q signals from the 70MHz IF. The I and Q signals are filtered and digitized. Finally, the digitized samples are sent to the baseband processor. The 1st down-conversion requires a local oscillation (LO) from 1920MHz to 1980MHz (the transmit band) so that the received frequency from 2110MHz to 2170MHz is converted to 190MHz. The 2nd down-conversion requires a LO at 260MHz to convert the 190MHz IF to the 70MHz IF. The LOs are generated by the synthesizer that will be discussed in Section 3.3.

Radio Design – Receiver

43

As mentioned in Section 2.9 of the system overview, the AFC is essential for precise demodulation and optimum detection. The AFC is a 140MHz local oscillator. The 140MHz LO is fed to the QPSK demodulator. The demodulator uses the 140MHz LO to recover the baseband I and Q signals. The nominal frequency of the AFC is 140MHz. The adjustable range of the frequency is ±2ppm and the frequency resolution of the adjustment is 0.03125ppm per step. The baseband processor commands the AFC with a 7-bit command code. The command code is a binary number between 0000000B and 1111111B (or 0 to 127 in decimal). The code 0000000B produces a –2ppm shift from 140MHz, while the code 1111111B produces a +2ppm shift. The drift also affects the transmit and LO frequencies.

The demodulator has a divide-by-two divider that divides the 140MHz LO to two 70MHz LOs. The two 70MHz LOs have a 90° phase difference. The in-phase LO is used to recover the I signal, while the quadrature LO is used to recover the Q signal.

The I and Q signals are separately filtered and digitized. The baseband filters are 0.22 roll-off, square root raised cosine filters. The sampling rate of the digitization is 32.768Msps. The digital samples are 8-bit long.

The adjacent channel selectivity, intermodulation selectivity, and the spurious response of the receiver were tested with continuous wave (CW) signals. The adjacent channel selectivity is required to be greater than 33dBc. The intermodulation selectivity and the spurious response are both required to be greater than 60dBc. The W-CDMA system provides twelve frequency channels for FDMA operation. Poor receiver selectivity results in interference from users at adjacent channels and limits the system performance.

As mentioned before, two identical receivers are installed in a radio to provide antenna diversity. The technical specifications apply to the both receivers.

The full specifications of the receivers are listed in Appendix A.

Radio Design – Receiver

44

3.2.3

3.2.3.1

Design Approach and Analysis

Receiver Noise Figure

The receiver must produces a BER of 10-3 at –113dBm or less input power level on the traffic channel. This received power level produces 6dB or greater Eb/No for the baseband processor to perform the detection. The traffic channel throughput is 128Kbps. The required noise figure can be found as follows [17].

The thermal noise, N, in communication receivers is modeled as an additive white Gaussian noise (AWGN) that is given be N = k ⋅ Te ⋅ B (watts)

(3.2.1)

where k

: is Boltzmann’s constant, 1.38x10-23 J/K.

Te

: is the effective system noise temperature in Kelvin.

B

: is the bandwidth in Hz.

Hence, the noise power spectral density, No, (noise power in 1 Hz bandwidth) is N o = kTe (W/Hz)

(3.2.2)

The bit energy, the bit period, the noise power spectral density and the received power are related by (3.2.3).

Eb Pr ⋅ Tb = No No

Radio Design – Receiver

(3.2.3)

45

where Tb =

1 : is the bit period or the reciprocal of the data rate. R

(3.2.2) and (3.2.3) are combined to obtain −1

E  1 Te = Pr ⋅  b  ⋅  No  k ⋅ R

(3.2.4)

or

E 10 ⋅ log(Te ) = Pr (dBW ) −  b  No

 (dB) − 10 ⋅ log(k ) − 10 ⋅ log( R) 

(3.2.5)

According to the specifications of the –113dBm received power and the 6dB Eb/No

Pr = −113 ⋅ dBm = −143 ⋅ dBW  Eb   = 6 ⋅ dB   No 

R = 128 ⋅ kbps

⇒ 10 ⋅ log( R) = 51 ⋅ dB

Te (dB) = −143(dBW ) − 6(dB) + 228.6(dBW / K − Hz ) − 51 = 28.6 ⋅ dB

or Te = 724.44 ⋅ K

The receiver noise figure, nf, is

nf = 1 +

Te = 3 .5 290

Radio Design – Receiver

or

NF = 5.4 ⋅ dB

46

3.2.3.2. Heterodyne Architecture and Spurious Analysis

The receiver uses a double-conversion superheterodyne front-end. The superheterodyne architecture helps to bring down high frequency signals at much lower intermediate frequencies (IF) so as to relax the Q requirement of the channel-select filter [18]. However, if the high frequencies are brought down to low frequencies in one conversion, image frequencies are difficult to reject at a satisfactory level from the image-rejection filter. Double-conversion allows a higher IF for the first conversion so that image suppression is easier. The second-conversion allows a lower IF for better channel selectivity. However, double-conversion introduces more image frequencies to the system. Figure 26 illustrates the superheterodyne architecture used in the receiver. 1st Mixer Duplexer 21102170 MHz

2nd Mixer

BPF LNA

BPF 190MHz

2110-2170MHz 1920–1980MHz

Figure 26.

70MHz

260MHz

Block diagram of the superheterodyne receiver.

Choosing IF Frequencies 190MHz and 70MHz were chosen to be the 1st ( f 1 _ IF ) and the 2nd ( f 2 _ IF ) IF frequencies respectively. The corresponding 1st ( f 1 _ LO ) and 2nd ( f 2 _ LO ) local oscillation (LO) frequencies are 1920-1980MHz and 260MHz respectively. This section explains the reasons for choosing these two IF frequencies. The 1st IF was chosen to match the channel offset of 190MHz between the transmitting and receiving bands. Therefore, the radio only needs one RF synthesizer. The output of the synthesizer can be used for the transmitter as well as the LO of the 1st downconversion of the receiver.

Radio Design – Receiver

47

The choice of the IF frequencies is based on the performance of the spurious response. Each down-conversion introduces an image frequency. The image can be mixed to the same IF as the desired signal. In considering the middle receiving channel of the WCDMA system, f RF = 2142.5MHz and f 1 _ LO = 1952.5MHz are the desired RF and 1st LO frequencies respectively. This is a low-side injection scheme because the 1st LO frequency is lower than the RF frequency. The 1st IF frequency is found by f 1 _ IF = f RF − f 1 _ LO ⇒

f 1 _ IF = 2142.5 − 1952.5 = 190 MHz

(3.2.6)

However, there is a frequency on the other side of the 1st LO frequency which produces the same 1st IF frequency. f 1 _ IF = f 1 _ LO − f 1 _ IMG ⇒

f 1 _ IMG = 1952.5 − 190 = 1762.5MHz

(3.2.7)

This frequency is the 1st image frequency. For the double-conversion receiver, there are two more image frequencies. The 2nd conversion is a high-side injection scheme because the LO frequency is higher than the input frequency. f 2 _ IF = f 2 _ LO − f 1 _ IF

(3.2.8)

The image frequency at the 2nd conversion is f 2 _ IF _ IMG = f 2 _ LO + f 2 _ IF ⇒

f 2 _ IF _ IMG = 260 + 70 = 330 MHz

(3.2.9)

The two additional image frequencies in the RF band are f 2 _ IMG = f 1 _ LO − f 2 _ IF _ IMG ⇒

f 2 _ IMG = 1952.5 − 330 = 1622.5MHz

(3.2.10)

f 3 _ IMG = f 1 _ LO + f 2 _ IF _ IMG ⇒

f 3 _ IMG = 1952.5 + 330 = 2282.5MHz

(3.2.11)

Radio Design – Receiver

48

Figure 27 shows these frequencies pictorially.

f f1_IF

f2_LO

f1_LO f2_IF_IMG

f2_IMG

fRF

f1_IMG

1st IF Band

f3_IMG

RF Band

f 2 _ LO = 260 MHz

f RF = 2142.5MHz

f 1 _ IF = 190 MHz

f 1 _ LO = 1952.5MHz

f 2 _ IF _ IMG = 330 MHz

f 1 _ IMG = 1762.5MHz f 2 _ IMG = 1622.5MHz f 3 _ IMG = 2282.5MHz

Figure 27.

Images of the double-conversion receiver

Removing the images depends on the choice of the IF frequencies and filters. If the 2nd IF frequency is chosen to be small, the 3rd image frequency is close to the desired RF band. The front-end filter has little rejection on the 3rd image. Therefore, the rejection of the 3rd image depends on the 1st IF filter which is the filter following the 1st down-conversion. The center frequency of this 1st IF filter is 190MHz.

Substitute (3.2.29) into (3.2.11) f 3 _ IMG = f1 _ LO + f 2 _ LO + f 2 _ IF

(3.2.12)

Substitute (3.2.8) into (3.2.6). The desired RF frequency is f RF = f 1 _ LO + f 1 _ IF = f 1 _ LO + f 2 _ LO − f 2 _ IF

Radio Design – Receiver

(3.2.13)

49

Then, the difference between the 3rd image frequency and the desired RF frequency is f 3 _ IMG − f RF = 2 ⋅ f 2 _ IF = 2 ⋅ 70 MHz = 140 MHz

(3.2.14)

The passband of the W-CDMA system is 60MHz. The above example is worked on the middle channel. The passband is ±30MHz about the middle channel. Therefore, the 3rd image frequency is outside the passband by 110MHz (=140-30MHz). The front-end filter can provide a good rejection to this 3rd image frequency. The subsequent 190MHz SAW filter also suppresses the image significantly. Many analog systems choose 455KHz as the 2nd IF. Technically, those systems allow the image in the RF passband and need the 1st IF filter to take care of the rejection. This approach requires high-selectivity 1st IF filters.

In addition to the images, there is an additional spurious response. It is called the half-IF response. It is due to the second harmonic generations of mixers. The 1st half-IF frequency at the 1st conversion is given by

f1 _ 1 = 2

1 1 ⋅ ( f RF + f 1 _ LO ) = ⋅ (2142.5 + 1952.5) = 2047.5MHz 2 2

(3.2.15)

and f RF − f 1 _ 1 = 2

1 1 1 ⋅ ( f RF − f 1 _ LO ) = ⋅ f 1 _ IF = ⋅190 = 95MHz 2 2 2

(3.2.16)

(3.2.16) reveals that the 1st half-IF frequency is away from the desired RF frequency by a half of the 1st IF frequency. The 1st half-IF spur is close to the receiver passband. The 2nd half-IF spur may produce the 2nd IF image which is given by (3.2.9).

Radio Design – Receiver

50

f2_1 = 2

1 1 ⋅ f 2 _ IF _ IMG + f 1 _ LO = ⋅ 330 + 1952.5 = 2117.5MHz 2 2

(3.2.17)

Substitute (3.2.6) and (3.2.9) into (3.2.17)

1 1 f RF − f 2 _ 1 = f 2 _ IF − ⋅ f 1 _ IF = 70 − ⋅190 = −25MHz 2 2 2

(3.2.18)

The 2nd half-IF frequency is in the receiver passband.

The half-IF spurs are close or in the receiver passband. The front-end filter may not reject it. Figure 28 shows the half-IF spurs and the system passband pictorially. The 2th-order distortion of the mixers must be minimized; otherwise, the half-IF spur can be significant. Balanced mixers, which suppress the even harmonics, are used in the radio to reduce some of the spurious mixing products. Receiver Passband 2110MHz

f1 _ 1 Figure 28.

2

f2_1

2

2170MHz

f RF

Half_IF spurs.

Computer analysis using the program called Spurious and Filter Analysis [19] was performed to verify the spurious response of the frequency plan. The simulation is based on the selected Mini-Circuit mixers (1st mixer SCM-2500 and 2nd mixer TUF-3SM) and filters (front-end duplexer designed and built by Dr. Sweeney, Soshin post-LNA filter and NDK 1st IF SAW filter).

Radio Design – Receiver

51

Table 7 shows the critical spurious of the frequency plan. The significant spurs on this table are the 2nd half-IF frequencies of 2117.5MHz and 2142.5MHz because they are in the receiver passband. Because of the non-ideal filter characteristic, the 2nd half-IF frequency of 2087.5MHz can be significant as well.

Table 7.

Critical spurious frequencies in the frequency plan.

Spurious

Bottom Channel

Middle Channel

Top Channel

2112.5 MHz

2142.5 MHz

2167.5 MHz

1st Image

1732.5

1762.5

1787.5

2nd Image

1592.5

1622.5

1647.5

3rd Image

2252.5

2282.5

2307.5

1st Half-IF

2017.5

2047.5

2072.5

2nd Half-IF

2087.5

2117.5

2142.5

Spurious and Filter Analysis can evaluate a single-conversion system. The inputs for the program are the device parameters and the system parameters. The device parameters are the frequency response of the filter and the mixing product table of the mixer. These parameters can be obtained from the manufacturer data sheets. The mixing product table provides the output levels of the mixer products. The mixer products are the frequencies of m ⋅ f RF ± n ⋅ f LO . The m and n are integers. The manufacturers provide the output levels in a quantity relative to the desired output of f RF ± f LO . The products are provided for m and n from 0 to 10. The system parameters are the desired RF frequency, the LO frequency and the target IF frequency. The program can find the RF spurs (or frequencies) which produce the target IF frequency, and the relative level of the spurs with respect to the desired RF frequency. Therefore, the spur attenuation of the conversion is obtained.

Since the program can only evaluate one conversion at a time, the analysis of a doubleconversion system has three parts. The first part is to evlauate the 1st conversion for the

Radio Design – Receiver

52

1st image and the 1st half-IF. The system parameters are the desired RF frequency ( f RF = 2142.5MHz ), the 1st LO frequency ( f 1 _ LO = 1952.5MHz ) and the 1st IF frequency ( f 1 _ IF = 190 MHz ) for the middle channel. The device parameters are the combined frequency response of the duplexer and the Soshin post-LNA filter, as well as the mixing product table of the Mini-Circuits SCM-2500 mixer. Appendix D-1 contains the result of this analysis. Figure 29 is a copy of Appendix D-1 and is shown here as an example. It shows all spurs associated with the 1st down-conversion process in the middle channel (2142.5MHz). The spurious attenuation is found to be at least 110dB. The rejections of the 1st image (1762.5MHz) and the 1st half-IF (2047.5MHz) are 110dB and 159.3dB respectively. The rejection is much larger than the 60dB minimum requirement. Therefore, the spurious response of the 1st down conversion meets the specifications.

1st Image

1st Half-IF

Figure 29.

Example of the part 1 spurious analysis (Appendix D-1).

Radio Design – Receiver

53

The second part is to evlauate the 1st conversion for the 2nd and 3rd images, and the 2nd half-IF. The system and device parameters are the same except the target IF frequency ( f 2 _ IF _ IMG = 330 MHz ). It is the image frequency associated with the 2nd conversion process. Appendix D-2 contains the analysis results and is shown here as Figure 30. It shows that the rejections of the 2nd (1622.5MHz) and 3rd (2282.5MHz) images are 110dB and 75.4dB respectively. They meet the specifications. The 2nd (2117.5MHz) half-IF rejection is 49dB. The 1st IF SAW filter must provide further rejection. The low 2nd halfIF rejection is because the 2nd half-IF falls in the receiver passband. This highlights the importance of IF SAW filters in rejecting the in-band spurious.

2nd Image

2nd Half-IF 3rd Image

Figure 30.

Example of the part 2 spurious analysis (Appendix D-2).

Radio Design – Receiver

54

The third part is to evaluate the 2nd half-IF rejection of the 2nd conversion. The system parameters are the desired 1st IF frequency ( f 1 _ IF = 190 MHz ), the 2nd LO frequency ( f 2 _ LO = 260 MHz ) and the 2nd IF frequency ( f 2 _ IF = 70 MHz ). The device parameters are the frequency response of the NDK SAW filter, and the mixing product table of the Mini-Circuits TUF-3SM mixer. Appendix D-3 contains the results of this analysis and is shown here as Figure 31. It shows that the 2nd conversion provides 40dB rejection to the image (330MHz). Therefore, the total rejection of the 2nd half-IF is 89dB and meets the specifications.

2nd IF Image

Figure 31.

Example of the part 3 spurious analysis (Appendix D-3).

Radio Design – Receiver

55

Similar computer analysis was carried on the bottom and top channels. The third part of the analysis is same to all channels because the 2nd conversion is channel independent. The analysis results on these channels can be found in Appendix D-4 through D-7. Table 8 summarizes the analysis results. The frequency plan meets the specifications on all channels.

Table 8.

Summary of the spurious rejection of the frequency plan.

Spurious Rejection

Bottom Channel

Middle Channel

Top Channel

2112.5 MHz

2142.5 MHz

2167.5 MHz

1st Image

110

110

110

2nd Image

150

150

150

3 Image

101.2

115.4

125.1

1st Half-IF

193.6

159.3

121.4

2nd Half-IF

131.7

89

89

in dB

rd

Channel Selectivity

The IF filters determine the channel selectivity of the radio. The filter bandwidth is equal to the 5MHz channel bandwidth. SAW filters are commonly used as IF filters because their high-selectivity frequency response. The receiver has two IF SAW filters at 190MHz and 70MHz. The adjacent channel rejections of the 190MHz 1st and 70MHz 2nd IF filter are 45dB and 50dB respectively. The total channel selectivity is 95dB; that is well above the specified 33dB channel selectivity.

3.2.3.3. Cascaded Receiver Chain Analysis

The receiver is a cascaded system with amplifiers, filters and mixers. The cascaded system has to meet the noise figure requirements, signal gain requirement, and intermodulation specifications simultaneously. The required noise figure is 5.4dB as discussed in Section 3.2.3.1. The cascaded gain should be large enough to bring up the

Radio Design – Receiver

56

signal from the specified minimum level (i.e. –113dBm) to a specified drive level of the demodulator. Intermodulation distortion is due to the non-linearity of the receiver, especially the 3rdorder distortion. Intermodulation distortion is harmful because the distortion is caused by the adjacent channel interferers. Since the interferers are in-band signals, the front-end filter provides no rejection. Consider a scenario that the receiver is detecting a weak signal that is accompanied by two strong interferers. The frequency of the desired signal is f s . The frequencies of the interferers are f i _ 1 = f s + ∆f , and f i _ 2 = f s + 2 ⋅ ∆f . ∆f is channel bandwidth. Figure 32 shows them pictorially.

∆f

fs

Figure 32.

∆f

fi_1

fi_2

Intermodulation interference.

The non-linearity of the receiver can be expressed as a power series (3.2.19). v o = a 0 + a1 v + a 2 v 2 + a 3 v 3 + .....

(3.2.19)

The first two terms ( a 0 + a1 v ) are the linear terms. The terms with power of 2 or more are the non-linear terms that create distortion.

The two interferers are represented by [20] v = cos wi _ 1t + cos wi _ 2 t

(3.2.20)

where wi _ 1 = 2πf i _ 1

Radio Design – Receiver

and

wi _ 2 = 2πf i _ 2

57

For simplicity, assume that the terms with power of 4 or higher of (3.2.19) are insignificant. Substituting (3.2.20) into (3.2.19) produces the following 3rd order products.

3 3 a 3 ⋅ cos(2wi _ 1 − wi _ 2 )t + a 3 ⋅ cos( wi _ 1 − 2 wi _ 1 )t + 4 4 3 3 a 3 ⋅ cos(2 wi _ 1 + wi _ 2 )t + a 3 ⋅ cos( wi _ 1 + 2 wi _ 1 )t + 4 4 1 1 a 3 ⋅ cos 3wi _ 1t + a 3 ⋅ cos 3wi _ 2 t ) 4 4

(3.2.21)

The third to sixth terms are three times the in-band frequency. They can be easily filtered, but the 1st and 2nd terms are the in-band products. Figure 32 shows that the 1st term falls on the desired signal. This is the intermodulation distortion. f 3rd _ dist = 2 ⋅ f i _ 1 − f i _ 2 = 2 ⋅ f s + 2 ⋅ ∆f − f s − 2 ⋅ ∆f = f s

(3.2.22)

If the desired signal is weak, the intermodulation distortion can corrupt the desired signal. According to the specifications, the level of the interferers producing the intermodulation distortion should be 60dB greater than the desired signal. This specification can be shown to be the determinant of the cascaded input intercept point.

The receiver is considered to have the same amplification for the weak desired signal and the strong interferers [18].

Psig _ out Psig _ in

≈

Pint_ out

(3.2.23)

Pint_ in

Since Pint_ out =

IIP3

2

Pint_ in

2

⋅ PIM 3 _ out

Radio Design – Receiver

(3.2.24)

58

where Psig _ in

: is the desired signal input power.

Psig _ out

: is the desired signal output power.

Pint_ in

: is the interferer input power.

Pont _ out

: is the interferer output power.

PIM 3 _ out

: is the output power of the 3rd-order intermodulation product.

IIP3

: is the cascaded input intercept point.

From (3.2.23) and (3.2.24), we have

Psign _ out PIM 3 _ out

IIP3 ⋅ Psig _ in 2

=

Pint_ in

(3.2.25)

3

For the same output level of the desired signal and the intermodulation distortion

Pint_ in Psig _ in

=

IIP3

2

Pint_ in

2

: is the intermodulation suppression.

(3.2.26)

In logarithmic scale

 Pint_ in   IM dB =  = 2 ⋅ IIP3 _ dB − 2 ⋅ Pint_ in _ dB P   sig _ in  _ dB

(3.2.27)

= 2 ⋅ IIP3 _ dB − 2 ⋅ IM dB − 2 ⋅ Psig _ in

Therefore

IIP3 _ dB =

3 ⋅ IM dB + Psig _ in 2

Radio Design – Receiver

(3.2.28)

59

The input power of the desired signal is defined from the minimum signal level

IIP3 _ dB =

3 ⋅ 60 − 113 = −23dBm 2

The 3rd order input interception point of the cascaded system should be –23dBm at least. Figure 33 shows the cascaded receiver chain of the radio.

DUP

ATT LNA

BPF RF

BPF MIX 1 AMP 1

IF 1

AMP 2

BPF MIX 2 AMP 3

Figure 33.

IF 2

AMP 4

Receiver chain of the radio.

The following equations can be used to evaluate cascaded systems [21].

M

Cascaded Gain:

G sys = ∑ Gi

in dB

(3.2.29)

in scale

(3.2.30)

in dB

(3.2.31)

i

Cascaded Noise Figure

nf sys

M −1 nf 2 − 1 1 = nf1 + + ..... + (nf M − 1) ⋅ ∏ g1 i gi

NFsys = 10 ⋅ log(nf sys )

where

g1 , g 2 ,....., g M

Radio Design – Receiver

: are the gain of individual blocks in scale.

60

Cascaded Output Intercept Point

M 1 OIP3 sys = −10 ⋅ log ∑  i oip3i ⋅ g i +1 ⋅ g i + 2 ⋅ ⋅ ⋅ ⋅ ⋅ g M

  

in dB

(3.2.32)

in dB

(3.2.33)

Cascaded Input Intercept Point IIP3 sys = OIP3 sys − G sys

The calculation can be performed with spreadsheet programs such as Excel. Table 9 is the spreadsheet for the cascaded receiver chain of Figure 33. The device parameters of each block are the gain, the noise figure and the 3rd order output interception point. They can be found in the data sheets. 3rd order output interception points of passive filters are large and are set to a hundred. The cascaded performances are 4.62dB for the noise figure, 46.94dB for the overall gain and –19.35dBm for the 3rd-order input intercept point. All of them meet to the design requirements.

Radio Design – Receiver

61

Table 9.

Cascaded receiver chain analysis. Device Parameters

Block DUP LNA ATT RF BPF MIX 1 AMP 1 IF 1 BPF AMP 2 MIX 2 AMP 3 IF 2 BPF AMP 4

Gain G, dB -2 23.7 -3.5 -2.5 -5.88 20.2 -18 20.2 -4.78 14 -8.5 14

Noise Figure

Output Intercept Point

NF, dB 2 1.9 3.5 2.5 5.88 4.3 18 4.3 4.78 5.2 8.5 5.2

OIP3, dBm 100 16 15 100 5 32.5 100 32.5 11 33 100 33

DUP

ATT LNA

Cascaded System Performance Input Intercept Point Noise Figure Gain NF, dB G, dB IIP3, dBm 2.00 -2 102.00 3.90 21.7 -5.70 3.91 18.2 -7.64 3.93 15.7 -7.64 4.06 9.82 -9.46 4.35 30.02 -9.73 4.45 12.02 -9.73 4.61 32.22 -10.15 4.62 27.44 -17.36 4.62 41.44 -17.88 4.62 32.94 -17.88 4.62 46.94 -19.35

BPF RF

BPF MIX 1

AMP 1

IF 1

AMP 2

Cascaded Output

BPF MIX 2 DUP - Duplexer LNA - HP Low Noise Amplifier ATT - M/A COM RF Attenuator AT-108 RF BPF - Soshin RF Bandpass Filter MIX 1 - Mini-Circuits SCM-2500 Mixer AMP 1 - Mini-Circuits ERA-5 Amplifier IF 1 - NDK 190MHz SAW Filter

Radio Design – Receiver

AMP 3

IF 2

AMP 4

AMP 2 - Mini-Circuits ERA-5 Amplifier MIX 2 - Mini-Circuits TUF-3SM Mixer AMP 3 - Mini-Circuits ERA-4 Amplifier IF 2 BPF - SAWTEK 70M SAW Filter AMP 4 - Mini-Circuits ERA-4 Amplifier

62

3.2.3.4

Automatic Gain Control (AGC)

The AGC dynamic range is specified to be 80dB. The entire 80dB range in one stage is difficult to obtain without compromising noise figure and intermodulation sensitivity. Equations (3.2.30) and (3.2.32) show that high gain at front-end devices gives good noise figure but produces poor 3rd-order intercept point and vice versa. Therefore, the 80dB control range of the AGC is broken into two parts. 40dB control is put on the front-end and the other 40dB is on the back-end. The AGC tracks the input signal, as it is going up from the minimum (-113dBm), with the 40dB control at the back-end. Therefore, the front-end can provide high gain without noise figure degradation. After the back-end AGC provides the 40dB control, the input signal is –73dBm. The system becomes intermodulation limited rather than noise figure limited. Then the following 40dB control at the front-end is activated. The front-end AGC keeps a constant stress level on the front-end devices and maintains the intermodulation distortion level. Analysis was performed to reveal the system performance with the intervention of the AGC. Figure 34 shows the results of the simulation.

Receiver In-Band Analysis 50

40

30

20

IF Amp Gain Reduction (dB)

10

RF Attenuation (dB) SNR (dB) Output IMD Ratio (dBc)

0 -120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

-20 Input Level (dBm)

Figure 34.

Simulation of the system performance over the AGC tracking range.

Radio Design – Receiver

63

The IF Amplifier Gain Reduction curve shows the increase of the attenuation from the back-end AGC as the input signal increases from –113 to –73 dBm. The front-end AGC (i.e. RF attenuation) takes over the gain control function from –73 to –33 dBm as shown by the RF attenuation curve.

Since the AGC gain reduction is put at the back-end of the receiver for a –113 to –73 dBm the input level, the system noise figure can be maintained. The signal-to-noise ratio (SNR) improves at the same rate as the input level as shown by the triangle curve. However, the Output IMD Ratio curve shows the increase of the intermodulation product as a result of increasing stress on the front-end devices. Further increase of the input level from –73dBm activates the front-end AGC. The SNR levels off at approximately 37dB and provides very good signal detection. After the attenuation is inserted at front-end, the stress level to the front-end devices is kept constant and causes no more intermodulation products.

It should be noted that the SNR is less than zero as the input range for –113 to –103 dBm. This is a result of the bandwidth needed to pass the spread spectrum of the W-CDMA system. As mentioned in Section 2.4 of the system overview, the bandwidth is 5MHz. The radio processes signals before despreading and hence the RF bandwidth must be 5MHz. A larger bandwidth means that more noise is present in the radio. However, after despreading done by the baseband processor, the noise bandwidth is restored back to (1+0.22)*128K=156.16KHz and the SNR increases. The SNR improvement is equal to the processing gain (PG) of the system. The PG is found to be 15dB in Section 2.3 of the system overview. For instance, at –113dBm input level, the SNR of the signal from the radio is –11dB as shown in Figure 34. After the despreading, the SNR of the signal is restored to 4dB.

Radio Design – Receiver

64

3.2.4

Circuit Level Design

Following the flow of the signal as shown in the block diagram in Section 3.2.1, the discussion of this section proceeds from the duplexer to the digital interface. The detailed schematics are in Appendix C-3, C-4 and C-5. The discussion of the circuits refers to the schematics for the component designators. The hardware implementation of the receiver comprises six assemblies. They are the duplexer, the receiver board, the demodulator board, the analog-to-digital (ADC) board, the AGC driver and the AFC board. Each assembly is discussed in following sub-section.

3.2.4.1

Duplexer – Receiver Part

This is the same duplexer mentioned in Section 3.1.4.5. The receiver part of the duplexer with designator U10, is shown in the schematic in Appendix C-3. Since the transmitter and the receiver share the same antenna for air interface, a physical path exists between the transmitter and the receiver. The transmitter delivers a high-power signal to the antenna. The high-power signal has to be isolated from the receiver very well; otherwise, the high-power signal drives the receiver into saturation and blocks the access of the desired small signal to the receiver. The duplexer is placed at the 1st stage of the receiver chain to isolate the high-power transmit signal and to pass the desired small signal to the receiver. It also provides part of the image rejection. It has 70dB rejection in the transmitting band and just 1.8dB loss to the receiving band. The operating band of the duplexer is 2110-2170MHz.

3.2.4.2 Receiver Board

The receiver board performs RF and IF signal processes such as amplification, downconversion and filtration. It receives the RF signal from the duplexer. It is a double downconversion reciver. The 1st stage converts the RF signal to a 190MHz 1st IF and the 2nd stage converts the 1st IF to a 70MHz 2nd IF. It includes the 40dB front-end AGC.

Radio Design – Receiver

65

Figure 35 is the block diagram of the receiver board. Its full schematic is shown in Appendix C-3.

2110-2170MHz RF in

LO 1 st

1 IF Stage

BPF AMP 2

IF 1

LNA

RF Stage

BPF AMP 1

MIX 1

ATT

RF

2nd IF Stage LO 2 70MHz IF out

BPF MIX 2

Figure 35.

AMP 3

IF 2

AMP 4

Block diagram of the receiver board.

Low Noise Amplifier (LNA)

The LNA should be high gain and low noise figure to compensate the tremendous insertion loss of the 1st IF SAW filter which insertion loss is 18dB. The HP MGA-86576 LNA (Appendix C-3: U1) was chosen for its high gain (23.7dB) and low noise figure (1.9dB). The recommended minimum 10Ω bias resistance (Appendix C-3: R10) is used at +5Vdc supply. The bias current is 13mA. The inductor (Appendix C-3: L10) works as an RF choke to isolate the DC supply line from high frequency signals. This is a 39nH choke and provides approximately 500Ω reactance. It is 10 times 50Ω. To optimize the noise figure or the sensitivity of the receiver, a small inductance 1.8nH (Appendix C-1: L11) is placed in series with the LNA input.

Radio Design – Receiver

66

Front-End Attenuator The front-end 40dB AGC is realized with an attenuator AT-108 (Appendix C-3: U2) from M/A COM. Its attenuation is controlled with a DC voltage from 0 to 5V on the pin 5. A 5V voltage gives a minimum attenuation of 3.5dB that is the intrinsic insertion loss of the attenuator. As the voltage increases, the attenuation increases until the total attenuation is 43.5dB (i.e. 40dB AGC attenuation plus the 3.5dB insertion loss).

RF Bandpass Filter (BPF)

The post-LNA filter (Appendix C-3: U30) is a dielectric filter from Soshin. Rejecting interferers solely by the duplexer demands a high selectivity filter design. The high selectivity filter design is associated with a drawback of high insertion loss. Since the duplexer is placed at the 1st stage of the receiver chain, its high insertion loss makes low noise figure receiver impossible. Therefore, part of the interference rejection is done after the LNA to allow low duplexer insertion loss for the sake of the receiver noise figure and to compensate the insufficient interference rejection of the duplexer. The filter prevents the transmitter power from saturating the mixer. This filter not only relaxes the duplexer requirement but also suppress the noise at the received image frequency. It has 30dB outband rejection and 2.5dB in-band insertion loss.

Mixers Mini-Circuits balanced diode mixers are used at the 1 st and 2nd down-conversion stages. The merits of these mixers are their predictable behavior, low harmonic generation, high port-to-port isolation, and high intercept point. The shortcomings are the high conversion loss and the need of high LO drives. Their shortcomings can be compensated easily by using amplifiers. On the other hand, their merits are the primary concerns for the radio.

Radio Design – Receiver

67

The 1st and 2nd down-conversion stages operate at different frequencies, leading to the use of different mixers. SCM2500 is used at the 1st conversion (Appendix C-3: U3) and TUF3SM at the 2nd conversion (Appendix C-3: U7). However, the design approach is the same for both.

The mixers are standard 50Ω devices. There is no special matching need for in-band signals. However, attention has to be paid to terminate out-band signals properly. This is done because out-band signals reflected back into the mixers can degrade the 3rd-order performance. Diplexers are put at the outputs of the mixers to terminate out-band signals. The diplexer is formed with a LC tuned circuit in series with a 50Ω resistor. The LC circuit is tuned to the in-band frequencies. Therefore, to the in-band signals, the diplexer looks like a high impedance device and has no interaction with the other circuits. To the out-band signals, the diplexer looks like a 50Ω resistor that gives termination to the signals and stops their reflection. The parts C30, L30, and R30 in the schematic in Appendix C-3 form the diplexers to the 1st mixer, and the parts C70, L70, and R70 form the diplexers to the 2nd mixers.

In addition to the diplexers, low pass filters (LPF) are put at the mixer outputs to remove the unwanted mixing products. The LPFs are 3-order Butterworth type. The parts of the LPF for the 1st mixer are L31, L32, and C31, while the parts of the LPF for the 2nd mixer are L71, L72, and C71. They are shown in the schematic in the Appendix C-3. Figure 36 depicts the circuit realization of the diplexers and LPFs.

Radio Design – Receiver

68

MIXER OUT

DIPLEXER/LPF OUT

Lf

Lf Cf

Ct

Lt

50

Figure 36.

Circuit realization of the diplexer and LPF.

Figure 37 and 38 are the Eclipse simulations of the frequency response and return loss of the diplexers and LPFs for the 1st and 2nd mixers respectively. The S21 curve shows the low pass response due to the LPF. The S11 curve shows the wide band termination (i.e. return loss > 10dB) due to the diplexer. Figure 37 and 38 show that the diplexers and LPFs for both the mixers have similar characteristics except the passband frequencies. F re q ue n c y R e s p on s e & R e tu rn L o ss o f D ip le x er a nd LP F fo r 1s t M ix er

0.00

-5.00

-10.00

-15.00

-20.00 S 21 F requ ency R espon se S 11 R eturn L oss -25.00

-30.00

-35.00

-40.00

-45.00 100.00

200.00

300.00

400.00

5 00.00

600 .00

700.00

800.00

900 .00

1000.0 0

F req u en cy (M H z )

Figure 37.

Frequency Response and Return Loss of Diplexer and LPF for 1st Mixer.

Radio Design – Receiver

69

Frequency Response & Return Loss of Diplexer and LPF for 2nd Mixer 0

-10

-20

-30 S21 Frequency Response S11 Return Loss -40

-50

-60

-70 0

100

200

300

400

500

600

700

800

900

1000

Frequency (MHz)

Figure 38.

Frequency Response and Return Loss of Diplexer and LPF for 2nd Mixer.

IF Filters

The IF filters set the channel selectivity and remove the half-IF interferers as identified in Section 3.2.3.2. NDK’s SAW filter was selected for the 190MHz 1st IF (Appendix C-3: U5). It gives 45dB channel selectivity or interference rejection. The filter’s shortcoming is its tremendous insertion loss of 18dB. This loss imposes a stringent requirement to the LNA. The 70MHz 2nd IF SAW filter (Appendix C-3: U9) is from SAWTEK. It gives another 50dB channel selectivity and interference rejection at the expense of 8.5dB insertion loss. Hence, the total channel sensitivity is 95dB.

Radio Design – Receiver

70

To use these filters effectively, attention must be paid to the impedance matching and the layout. Improper matching at the input and output ports of the filters causes serious distortion of the passband characteristics of the filters. Improper layout produces too much board feed-through and the out-band attenuation characteristics of the filters cannot be predicted. The filters’ data sheets provide the topologies and values of the matching components, as well as recommended layout patterns. It is important to point out that the filters are not symmetrical with respect to required matching networks.

Amplifiers

As in the modulator board of the transmitter (Section 3.1.4.2), Mini-Circuits ERA monolithic amplifiers are used as gain blocks in the receiver. Devices were chosen to make the compromise between noise figure, gain and intermodulation sensitivity. Four gain blocks are distributed along the chain according to the results from Section 3.2.3.3. Two of them are ERA-5 (Appendix C-3: U4, U6) at the 190MHz 1st IF stage, which are used for their high gain. The other two are ERA-4 (Appendix C-3: U8, U10) at the 70MHz 2nd IF stage where lesser gain is favorable.

The bias RF chokes were chosen such that their reactance is at least 500Ω. Based on this criterion, a 1uH (Appendix C-3: L41, L60) choke was used for the ERA-5 and a 1.8uH chokes (Appendix C-3: L82, L102) was used for ERA-4.

As mentioned in Section 3.1.4.2, the amplifiers should be biased with a supply voltage higher than the device voltages for a low variation of the bias condition against temperature. A 7V supply was chosen. The bias resistance is calculated with the equation (3.1.9) shown in Section 3.1.4.2. The bias resistance for the ERA-5 is 32Ω. Two 16Ω resistors are connected in series to produce the 32Ω resistance (Appendix C-3: R41, R42, R60, R61). This approach allows the bias power to be shared between the two resistors and to relax the power handling requirement of each resistor. The bias resistance for the

Radio Design – Receiver

71

ERA-4 is 24Ω. Two 12Ω resistors are connected in series to produce the 24Ω resistance (Appendix C-3: R82, R83, R102, R103).

3.2.4.3

Demodulator Board

The IF amplifier, back-end AGC, and demodulator are contained in a RF2667 device from RF Micro Devices (RFMD). The RFMD evaluation board for the RF2667 was used. The evaluation board contains all the required support circuitry. There are three devices in the board. One is the RF2667. The other two are the wideband operational amplifiers (CLC426-CL) from National Semiconductor. The amplifiers provides voltage gain to the I and Q baseband outputs of the demodulator chip. Figure 39 is the block diagram of the board. RFMD 2667 1Vpp BB AMP 17.7dB

+45°

AGC AMP

÷2 BB AMP 17.7dB

-45°

1Vpp

Figure 39.

Block diagram of the demodulator board.

The RF2667 chip demodulates the 70MHz IF signal for the baseband signals. It contains an IF amplifier and an IQ demodulator. The IF amplifier is gain controllable. The IF amplifier allows 100dB of gain control range by varying gain from -50 to 50dB. The back-end AGC utilizes the control range of the amplifier from 10dB to 50dB. The gain is controlled by voltage.

Radio Design – Receiver

72

After the IF amplifier, there is the IQ demodulator where the baseband signal is recovered from the IF signal. The LO signal injected into the demodulator has a frequency of 140MHz. The LO signal is divided by two and split into two 70MHz LOs. One is shifted by 45° and fed to the in-phase arm of the demodulator. The other one is shifted by -45° and fed to the quadrature arm. The demodulator extracts the in-phase and quadrature signals from the IF signal through the down-conversion process.

The demodulator outputs are amplified to 1Vpp by the baseband amplifiers. The 1Vpp is the specified input range of the ADC. The gain of the baseband amplifiers in the evaluation board was set to 17.7dB to produce the 1Vpp output.

3.2.4.4

ADC Board

The ADC board is the AD9059 evaluation board from Analog Devices. It performs the analog-to-digital conversion for the digital format of the baseband signals to facilitate the digital processing in the processor. The level of the baseband signals is kept at 1Vpp through the AGC tracking. The 1Vpp level allows better utilization of the dynamic range of the ADCs. The AD9059’s are capable of 60Msps but actually operate at 32.768Msps.

3.2.4.5

AGC Driver

There are two identical AGC drivers, one for each receiver. Both drivers are on one board. Figure 40 is the block diagram one driver and the full schematic is shown in Appendix C-4. Front-End Driver DAC

Buffer Back-End Driver

Figure 40.

Analog Voltage Output to Receiver Board

Analog Voltage Output to Demodulator Board

AGC driver block diagram.

Radio Design – Receiver

73

The driver accepts a digital command from the baseband processor and provides a corresponding analog voltage to drive the back-end and front-end attenuators. Since there are two AGCs, the driver is designed to have two channels. As mentioned in Section 3.2.2, the gain control is 1dB per step and the range is 80dB. The digital command is code is a binary number between 0000000B and 1010000B (or 0 to 80 in decimal). An Analog Devices AD557 DAC (Appendix C-4: U1 or U3) is used as the interface between the processor and the AGC driver. Based on the control characteristics of the ADC, RFMD RF2667 and M/A COM AT-108, and the control sequence of from the back-end AGC to the front-end AGC as signals going low to high, the driver has to map the command code to the analog voltage according to Table 10.

Table 10.

Mapping table of the command code to driver voltage

RF In (dBm)

Command

AD557 Out (V)

RF2667 Drive (V)

AT-108 Drive (V)

-113

0000000

0.01

2.5

5

-73

0101000

0.81

1.6

5

-33

1010000

1.61

1.6

0

The DAC is 8-bit device that has one bit more than the command digits. In order to fully utilize the output range of the DAC, the command digits are tied to the most significant 7-bits of the DAC and the least significant bit is held high. Thus, the command is effectively multiplied by a factor of 2 and the output voltage of the DAC is from 0.01 to 1.61V. The 10mV residual voltage is a result of the least significant bit being tied high. An operation amplifier (Appendix C-2: U7A or U7B) configured as the voltage follower is placed at the DAC output.

The back-end AGC of the RF2667 is activated in the region of low input levels. The relationship between the command code and the gain is inversely proportional. This means that a low command value causes a high gain. This driver has two stages to realize the mapping shown in Table 10. The 1st stage is a non-inverted amplifier (Appendix C-4:

Radio Design – Receiver

74

U2B or U4B) that drives the 2nd stage and a diode limiter. The diode (Appendix C-4: D1 or D2) is used to limit the output of the 1st stage. The 2nd stage is an inverted amplifier (Appendix C-4: U5A or U5B) to produce the phase inversion and the level shifting. The back-end driver voltage is limited at 1.6V as the DAC output goes higher than 0.8V because of the diode limiter. A variable resistor (Appendix C-4: R29 or R30) is used to facilitate the level shifting adjustment because of the high gain-to-voltage sensitivity of RF2667 (i.e. 40dB/0.9V=44.4dB/V).

The front-end AGC by AT-108 is activated as the DAC output goes higher than 0.8V. This driver provides phase inversion as well. However, the design of this driver is relatively simple because there is no limiting voltage. A single inverting amplifier (Appendix C-2: U2 or U4) is sufficient. There is no level shifting adjustment required because the gain-to-voltage sensitivity of AT-108 is small (i.e. 40dB/5V=8dB/V). However, using the operational amplifier for 5V output swing with a 5V supply demands rail-to-rail amplifiers. A National Semiconductor LM6132 was selected. Figure 41 is the PSPICE simulation of the drivers. The driver characteristics match Table 10 very well. The drivers have very linear characteristics over their control regions. The 1.6V limited voltage of the back-end AGC driver is well defined. AGC Driver Characteristic

Driver Output Voltage (V)

Front-end

Back-end

DAC AD557 Output Voltage (V)

Figure 41.

AGC driver characteristics.

Radio Design – Receiver

75

3.2.4.6

AFC Board

The AFC board includes the transmit power control (TPC) that has been described in Section 3.1.4.3. It provides the local oscillators (LO) for the 70MHz IF demodulation. The baseband processor commands the AFC board through DAC devices to adjust the oscillation frequency. Figure 42 is the block diagram of the AFC board and the full schematic is shown in Appendix C-5.

DAC

AFC Driver

VCTCXO

x14 Multiplier

Splitter

To Synthesizer

BPF AMP

to Main Receiver

to Diversity Receiver

VCTCXO - Voltage Controllable Temperature Compensated Crystal Oscillator BPF - Bandpass Filter AMP - Amplifier

Figure 42.

AFC block diagram.

The dual receiver architecture requires two 140MHz LOs, one for the main and one for the diversity receiver. However, in contrast to the VGC drivers, it is not necessary to have independent LOs because the signals intercepted by the diversity antenna may be different in amplitude and phase but not frequency. Thus, the AFC just has one signal generation circuit. At the final stage, the generated signal is split into two LOs with a Mini-Circuits splitter (Appendix C-5: U9).

A voltage controllable temperature compensated crystal oscillator (VCTCXO) (Appendix C-5: U12) with high tuning linearity from Oscillatek is the tuning element in the AFC. The VCTCXO not only serves the AFC but also provides the reference frequency to the synthesizer. Therefore, the frequency tuning affects the transmit frequency and the receiver LO frequencies produced by the synthesizer. The normal oscillation frequency of

Radio Design – Receiver

76

the VCTCXO is 10MHz. In order to get 140MHz, the 10MHz signal is fed to the inverters. The inverters operate as non-linear amplifiers (Appendix C-5: U3) and generate the harmonics. A high frequency selective TOKO filter (Appendix C-5, U8) removes the harmonics except the 140MHz signal. Since the filter is a 50Ω device, three inverters are connected in parallel to lower their output impedance or to increase the driving capability. Finally the 140MHz signal is amplified and split. The amplifier (Appendix C5: U4) is the Mini-Circuits ERA-1 monolithic amplifier. The splitter (Appendix C-5: U9) is the Mini-Circuits LRPS-2-1 1-to-2 splitter.

An Analog Devices AD557 DAC (Appendix C-5: U1) is the interface between the AFC board and the processor. The command code from the process is 7 bits long. The bits are tied to the most seven significant bits of the DAC. The least significant bit of the DAC is held high. Effectively the command code is multiply by a factor of 2. A two-stage amplifier (Appendix C-5: U2A,B) processes the DAC output for the tuning voltage to the VCTCXO. The VCTCXO has a measured ±10ppm frequency deviation at 2.5V ±1.5V. The tuning range required by the system is ±2ppm over the command range 0~127 (or 0~1111111B). This 2ppm tuning effect applies to all the output frequencies – the transmit signal, the 1st and 2nd LOs, and the 140MHz LO for the demodulation. Thus the amplifier maps the DAC output to a narrower tuning voltage as shown in Table 11.

Table 11.

Mapping table of the digital command to tuning voltage.

Command

AD557 Out (V)

Tuning Voltage

0000000

0

2.2

0111111

1.26

2.5

1111111

2.54

2.8

Radio Design – Receiver

77

3.3

Synthesizer

The synthesizer provides the local oscillators (LO) used in the radio. There are two LO synthesizers. One of the synthesizers produces the LO frequency at the transmitting band (1920-1980MHz). It is the RF synthesizer. The output of this synthesizer is split into three outputs, one for the transmitter modulator and the other two outputs are the first LO for each receiver. The other synthesizer produces an LO frequency at 260MHz. Its output is split for the 2nd down-conversion of the two receivers.

The synthesizer consists of three units: the synthesizer board, the splitter board and the 10MHz voltage controllable temperature compensated crystal oscillator (VCTCXO). The VCTCXO is on the AFC board. The VCTCXO supplies the reference frequency for the synthesizer.

The synthesizer is a modified Harris HFA3524 evaluation board. The synthesizer board contains a Harris HFA3524 dual phase-lock-loop (PLL) chip. It provides the simultaneous radio frequency (RF) and intermediate frequency (IF) LO generation.

The splitter board splits and distributes the outputs of the synthesizer board to different parts of the radio. Figure 43 is the block diagram of the synthesizer.

Radio Design – Synthesizer

78

3.3.1

Block Diagram

VCTCXO ÷R

Synthesizer Board

RF

divider Phase Comparator

Loop Filter

ATT

VCO

÷NR divider

RF

Splitter Board

to Transmitter

ATT AMP

to Main Receiver

Splitter

Splitter

ATT

ATT

to Diversity Receiver

AMP IF Splitter

to Main Receiver

ATT

to Diversity Receiver

AMP

IF Phase Comparator

Loop Filter

VCO

LPF

ATT

÷NI divider VCO - Voltage Controllable Oscillator LPF - Low Pass Filter AMP - Amplifier ATT - Attenuator

Figure 43.

Synthesizer block diagram.

Radio Design – Synthesizer

79

3.3.2

Technical Specifications

The RF synthesizer is programmed for the transmitting frequencies from 1922.5 to 1977.5 MHz in 5MHz increments. The IF synthesizer provides a fixed frequency LO at 260MHz. The requirements for the two synthesizers are different but the design approach and the PLL architecture for each are the same. The discussion of the PLL architecture is based on the RF synthesizer; however the discussion is applicable to the IF synthesizer as well. The differences will be noted.

The 10MHz VCTCXO output is divided by four to obtain a 2.5MHz reference frequency for the RF and IF synthesizers. The frequency accuracy of the synthesizer outputs is equal to the accuracy of the VCTCXO output. The VCTCXO has a trim adjustment to facilitate the frequency setting. The frequency accuracy is set within ±1ppm to comply with the specifications. It also has an electronic adjustment for the AFC. The AFC may tune the VCTCXO ±2ppm from the nominal frequency. Therefore, the RF and IF synthesizer outputs can accommodate a ±2ppm frequency drift.

The splitter board amplifies and splits the LOs from the synthesizer board. The LO power level for the transmitter is –1dBm. This level is within the specified LO drive level of the RF2242 modulator device. The 1st LO power level for the SCM-2500 mixers of the receivers is 7dBm. The 2nd LO power level for the TUF-3SM mixers is 10dBm.

3.3.3 Synthesizer Board

3.3.3.1

Design Modifications

The component designators used in the discussion of this section refer to the schematic shown on the Harris application note AN9630 [22].

Radio Design – Synthesizer

80

RF Synthesizer Modification

The RF synthesizer was originally designed for the 2132-2204 MHz frequency band [22]. The RF VCO was replaced with Zcomm SMV1960L for the desired operational band (1920-1980 MHz). The output attenuation pad was changed from -8dB to -2dB for 8dBm output power. Figure 44 shows the block diagram of the RF synthesizer and indicates the modified parts. Modified parts

RF Synthesizer

VCTCXO

÷R

Phase Comparator

Loop Filter

VCO

19201980 MHz 8dBm ATT

÷NR divider

Figure 44.

RF synthesizer block diagram and the modifications.

IF Synthesizer Modification

The IF oscillator, which is built on board, was modified from the original 560MHz oscillation frequency to the desired 260MHz. The oscillator is a common collector Colpitts oscillator. Figure 45 shows the oscillator with the frequency determining components.

Radio Design – Synthesizer

81

L1

L

Loop Filter, V t C2 Cv

Ca C1

Figure 45.

Re

Frequency determining components of the Colpitts oscillator.

The oscillation frequency is determined by the circuit inductance (L) and capacitance (C).

fo =

1

(3.3.1)

2π ⋅ L ⋅ C

where L = L1 −

C=

1 (2π ⋅ f o ) ⋅ (C v + C a ) 2

C1 ⋅ C 2 C1 + C 2

(3.3.2)

(3.3.3)

C v is the capacitance developed by the varactor diode. It changes the capacitance, C v , based on the bias voltage from the loop filter. Thus, the oscillation frequency changes until the PLL locks to the target frequency of 260MHz. C a provides a fine tune to the oscillator. C1 and C 2 form a capacitive voltage divider to derive a feedback from the output to the base-emitter junction of the transistor. A closed oscillation loop is established. C1 and C 2 are in series to give the circuit capacitance.

Radio Design – Synthesizer

82

Evaluating (3.3.3) with C1 = C 2 = 15 pF results in C = 7.5 pF . Evaluating (3.3.1) with C = 7.5 pF and f o = 260 MHz results in L = 50nH .

Referring to the data sheet of the varactor, C v is estimated to be 20pF. Evaluating (3.3.2) with L = 50nH , C v = 20 pF , C a = 4.7 pF and f o = 260MHz results in L1 = 65nH . A standard value, 68nH was chosen for L1 .

Additionally, the RF (L2) choke for the oscillator was changed from 12nH to 680nH to give better isolation to the power supply. The IF oscillator is followed with a three-section, π-Butterworth low pass filter (LPF). It is used to suppress the harmonic output from the oscillator. It was modified for the cutoff at 350MHz. Figure 46 shows the block diagram of the IF synthesizer and indicates the modified parts.

IF Synthesizer

VCTCXO

÷R

Phase Comparator

Modified parts Loop Filter

VCO

LPF

ATT

260 MHz 7dBm

÷NI divider

Figure 46.

IF synthesizer block diagram and the modifications.

Miscellaneous Changes

In order to unify the power supplies for the radio, the supply voltage of the synthesizer board is 5V which is different from the original 3V design. This change requires the

Radio Design – Synthesizer

83

change of the PLL control signal levels (LE, Clock and Data). The resistors of RA23, RA24, and RA25 were changed from 10KΩ to 5.1Ω to obtain the level shift.

The chosen VCTCXO is transistor-transistor-logic (TTL) compatible output. Therefore, the 50Ω termination (RREF ) at the reference input of the synthesizer board was removed.

As a summary, Table 12 lists all the changes of the components on the synthesizer board that were made to comply with the requirements of the radio.

Table 12.

Component changes on the Harris synthesizer board.

Part Designator

Was

Is

Change for

VCO

Z-Comm

Z-Comm

RF Synthesizer

SMV2100L

SMV1960L

L1

12 nH

68 nH

IF Synthesizer

L2

12 nH

680 nH

IF Synthesizer

LF1

12 nH

39 nH

IF Synthesizer

CF1

5.6 pF

8 pF

IF Synthesizer

CF2

5.6 pF

8 pF

IF Synthesizer

RA4

20 Ω

5.5 Ω

RF Synthesizer

RA5

20 Ω

5.5 Ω

RF Synthesizer

RA6

51 Ω

220 Ω

RF Synthesizer

RA21

10 KΩ

5.1 KΩ

5V Supply

RA23

10 KΩ

5.1 KΩ

5V Supply

RA25

10 KΩ

5.1 KΩ

5V Supply

RREF

50 Ω

Nil

VCTCXO TTL Output

Radio Design – Synthesizer

84

3.3.3.2

Loop Filter

The loop filter is the most important part of the PLL design. It is the part available for designers to optimize the PLL performance, as the other parts are off-the-shelf components.

The loop filter was designed to obtain a 25KHz loop bandwidth and the 45° phase margin. The 25KHz loop bandwidth is a hundredth of the 2.5MHz loop reference. This provides good suppression of the reference and eliminates the modulation sidebands. The radio stays on the channel over the course of a conversation. Therefore, the lock in time of the loop is not a critical requirement. The stability of the loop becomes the design criterion. The phase margin of the loop provides the stability and was chosen to be 45°. The loop was chosen to be type-2, 4th-order. The required loop filter is shown in Figure 47. R2 From Charge Pump - I

To VCO - V

R1

C2

C0 C1

Figure 47.

The realization of the loop filter.

The transfer function for the loop filter is given by

K f ( s) =

sR1C1 + 1 s [ s R1 R2 C 0 C1C 2 + s ( R1C 0 C1 + R2 C 0 C 2 + R2 C1C 2 + R1C1C 2 ) + C 0 + C1 + C 2 ) 2

2

(3.3.4)

Radio Design – Synthesizer

85

The detailed design procedure of a PLL can be found in [23]. Figure 48 and 49 are the simulated gain and phase response of the loop respectively. Loop Gain Response Comparison 100 80

Magnitude of G(s)H(s) in dB

60 40

Loop Bandwidth ≈30KHz

20 0 -20 -40

2.5MHz Reference Suppression > 80dB

-60 -80 -100 2 10

Figure 48.

3

4

10

5

6

10 10 Frequency in Hz

10

7

10

Gain response of the type-2, 4th-order loop. Loop Phase Response Comparison

-140

Phase Margin ≈38°

Phase of G(s)H(s) in Degree

-145 -150 -155 -160 -165 -170 -175 -180 2 10

3

4

10

10

5

10

Frequency in Hz

Figure 49.

Phase response of the type-2, 4th-order loop.

Radio Design – Synthesizer

86

The simulation is based on the loop response for the middle channel (1952.5MHz). The choice of the channel affects the N-divider values of the PLL. The divider values to program the PLL is given in Appendix E. The use of the standard component values produces the performance deviation between the target and simulation. The deviation is small and is not a problem. No potential instability of the loop was experienced in the laboratory evaluation.

3.3.4

Splitter Board

The splitter board has the RF and IF channels, and supplies the LOs at specified power levels and provides adequate reverse isolation. The full schematic is in Appendix C-6.

3.3.4.1

RF Channel

Figure 50 is the block diagram of the RF channel. RF ATT

ATT AMP -20dB

Figure 50.

20dB

to Transmitter -1dBm

-4dB Splitter

7dBm

Splitter

from the RF Synthesizer

ATT -4dB

-4dB

AMP 12dB

-4dB

to Main Receiver 7dBm to Diversity Receiver 7dBm

RF channel block diagram.

As shown in Figure 50, the RF synthesizer output level is 7dBm. The RF2422 modulator requires an LO power between –3 and 3dBm. The splitter is designed to deliver -1dBm to the transmitter. The splitter supplies the LOs at 7dBm to the receiver 1st mixer.

The first two stages of the channel are a 20dB attenuator (Appendix C-6: R350-352) and a 20dB gain block (Appendix C-6: U35). They provide a reverse isolation between the synthesizer and the modulator. Without the buffer, the modulation process in the

Radio Design – Synthesizer

87

modulator caused a disturbance at the VCO output of the RF synthesizer. The loop will not compensate for any disturbance outside the loop bandwidth. The modulation sidebands of the disturbance developed at the synthesizer output. Since the receivers share the same synthesizer output, these sidebands became a noise source to the receivers. The attenuator and the gain block provide a total of 43dB reverse isolation. The ERA-3SM was selected for its small reverse transmission (S12= –23dB).

Mini-Circuits LRPS-2-25 splitters were selected. One-to-two splitting causes the output to be 3dB lower than the input. The splitter has 1dB insertion loss. Therefore, the total signal attenuation of the splitter is 4dB. A splitter (Appendix C-6: U30) divides the RF signal into two outputs. One output is attenuated by 4dB (Appendix C-6: R300-302) and supplied to the transmitter modulator as shown in the upper chain of Figure 50. The power level of this output is –1dBm. The other output is further divided by a splitter (Appendix C-6, U32) into two to supply the two receivers as shown in the lower chain of Figure 50. A Mini-Circuits ERA-1SM amplifier (Appendix C-6: U33) compensates the loss due to the attenuator (Appendix C-6: R310-312) and the splitters so that the output power of the two outputs is 7dBm.

3.3.4.2

IF Channel

The IF channel provides one-to-two splitting for the IF synthesizer output. This channel has 2dB gain so that the IF LOs are 10dBm. Figure 51 is the block diagram of the IF

from the IF Synthesizer

ATT

8dBm

AMP -6dB

Figure 51.

Splitter

channel.

12dB

-4dB

to Main Receiver 10dBm to Diversity Receiver 10dBm

IF channel block diagram.

Radio Design – Synthesizer

88

The splitter (Appenidx C-6: U33) is different from the splitter used in the RF channel because the IF frequency is much lower than the RF frequency. The splitter is MiniCircuits LRPS-2-1. The splitter causes 4dB signal attenuation. The resistive attenuator (Appendix C-6: R330-331) is a 6dB pad and the same ERA-1SM amplifier (Appendix C6, U33) is used as the gain block. The total gain of the channel is 2dB; therefore, an 8dBm input produces a 10dBm output.

Radio Design – Synthesizer

89

4. Radio Performance

This chapter presents the performance of the radio.

4.1

Transmitter

4.1.1

Transmit Power

W-CDMA test signals were not available. Therefore, the transmit power is measured on the continuous-wave (CW) output. The QPSK modulation is equivalent a single-sideband generator, if the direct (I) and quadrature (Q) signals are the same but the I signal leads the Q signal by 90°. A modulation generator was built as shown in Figure 52 for generating the test carrier. The generator produces two TTL compatible square waves. The square waves are 90° out-of-phase. The frequency of the square waves is 1.25MHz which is inside the passband of the baseband filters.

20MHz CLK

I +5V

+5V 1.25MHz

10K

+5V

+5V

1 0 1

2

3

4

12 11

74HCT04

D

P R C L

+5V

12

4 Q

9

2 3

CLK

74HCT04

1 0

Q

D

Q

5

11

D

C L

C L Q

6

74HCT74 +5V

P R

Q

9

+5V

2 3

CLK

CLK

8

1 74HCT74 3

P R

4

Q

D

C L

8

1 74HCT74 3

P R

Q

5

Q

CLK Q

6

74HCT74 +5V

1

1

20MHz 33pF

Figure 52.

33pF

Modulation generator.

The square waves are fed to the DAC board of the transmitter. The phase-lead square wave is applied to the I channel DAC. All the input pins of the DAC are tied together. This provides the codes between 00000000B and 11111111B to the DAC. The output of the DAC is a 0.5V square wave. The baseband filter removes the harmonics of the DAC output and provides a 1.25MHz tone signal. Similarly, a 1.25MHz tone, which is 90° phase lag, is generated on the Q channel. Radio Performance

90

The two tones are fed to the transmitter modulator to generate the single-sideband CW output. The CW output is 1.25MHz away the modulator LO as shown in Figure 53. After the power amplification, the CW output can be measured for the transmit power. Figure 54 shows the measurement setup.

1.25MHz DAC

LPF

Local from Synthesizer

90°

+45° -45°

fo DAC

fo

fo + 1.25MHz

LPF

1.25MHz

Figure 53.

Single-sideband generation.

Modulation Generator

Computer

Figure 54.

Spectrum Analyzer

Transmitter

TPC Code Generator

Transmit power test setup.

The computer is used to load the commands to the synthesizer for setting the channel of the radio. The test is conducted on the middle channel. The TPC code generator provides the command code to set the transmit power level. The modulation generator provides the signals for the single-sideband generation. The spectrum analyzer measures the transmitter output.

Radio Performance

91

Measurement Procedure:

1.

Set the transmitter to operate on the middle channel (i.e. 1952.5MHz).

2.

Set the TPC command code for 0 (i.e. 0000000B binary).

3.

Adjust the variable resistor (Appendix C-5: R18) in the AFC board for the maximum transmit power, approximately 32dBm.

4.

Set the TPC command code for 70 (i.e. 1000110B binary).

5.

Adjust the variable resistor (Appendix C-5: R19) in the AFC board for the 70dB transmit power attenuation.

6.

Repeat the procedure 2 to 5 until the maximum transmit power and the 70dB transmit power attenuation are simultaneously obtained.

7.

Measure the single-sideband output with the spectrum analyzer for the transmit power.

Figure 55 shows the output spectrum of the transmitter.

31.85dBm = 1.53W

-25dBc -26dBc

-31.5dBc

-34dBc -57dBc

-2.5MHz

-1.25MHz

fo

+1.25MHz

+2.5MHz

+3.75MHz

fo = 1952.5MHz

Figure 55.

Transmitter output power spectrum.

The output power meets the specification of 1.6W +20% -50%. This is the measured data of the single-stage power amplifier design. This design can provide sufficient transmit power but fails the adjacent channel power specification.

Radio Performance

92

Figure 56 shows the test setup for the adjacent channel power measurement. Figure 57 is the measured spectrum of the QPSK modulated transmit signal. I modulation Spectrum Analyzer

Transmitter

Signal Generator Q modulation

TPC Code Generator

Computer

Figure 56.

Adjacent channel power test setup.

Spectrum of QPSK ModulatedTransmit Signal 0

-25dBc

-10

-20

5MHz

-30

-40

-50

-60 -12.5

-7.5

-2.5

2.5

7.5

12.5

Offset Frequency (MHz) from 1952.5MHz (Middle Channel)

Figure 57.

The measured spectrum of the QPSK modulated transmit signal.

The signal generator is HP4433B. The generator is an RF signal generator but it also provides the analog I and Q filtered baseband signals at its back panel. The symbol rate was 4.096Msps and the 0.22 roll-off square root raised cosine pulse shaping was applied on the symbols. Since the baseband signals were in analog form, the signals were fed to

Radio Performance

93

the transmitter modulator instead of the digital interface. The modulator output was set to –2dBm to minimize the adjacent channel power generated by the single-stage power amplifier. The modulator output less than –2dBm could not deliver the required transmit power. However, the adjacent channel power was –25dBc as shown in Figure 57. The adjacent channel power is higher the specification of –40dBc.

A two-stage power amplifier design is being considered to improve the adjacent channel power suppression as mention in Section 3.1.4.4. The design improvement is in progress. The test data is not available at the time of this writing.

4.1.2

Transmit Power Control (TPC)

The test setup in Figure 54 is applicable to this measurement.

Measurement Procedure:

1. Set the transmitter to operate on the middle channel (i.e. 1952.5MHz). 2. Set the TPC command code for 0 (i.e. 0000000B binary) for the maximum transmit power. 3. Record the transmitter output power and the power control voltage. 4. Increase the TPC command code by 10. 5. Repeat the procedure 3 to 4 until the command code is 70 (i.e. 1000110B binary).

Figure 58 is the measurement results.

Radio Performance

94

Transmit Power Control (TPC) Characteristics 40

4.5

30

4

20

3.5

10

3

0

2.5 Tx Pwr (dBm) Pcont (V)

-10

2

-20

1.5

-30

1

-40

0.5

-50

0 0

10

20

30

40

50

60

70

Command Code (0-70)

Figure 58.

Transmit power control characteristic.

The transmit power control voltage curve (Pcont) shows that the transmit power control voltage responds to the command code linearly, while the transmit power curve (Tx Pwr) shows that the transmit output power responds to the command code non-linearly. The transmit power behaves non-linearly because of the non-linear attenuation-to-voltage characteristic of the AT-108 attenuators. However, the transmit output power has a monotonic decrease characteristic. The objective of the power control can be performed. Also, the control range meets the 70dB specification.

Radio Performance

95

4.2

Receiver

4.2.1

Receiver Noise figure

Without the W-CDMA base station, it is not possible to do a direct measurement of sensitivity. Therefore, the minimum detectable signal (MDS) is measured to estimate the noise figure of the receiver. The MDS is an RF input level at the receiver so that the receiver analog output is equal to the noise output. The noise figure can be approximately estimated by NF (dB ) = MDS (dBm) + 174(dBm) − 10 ⋅ log B (dB )

(4.1)

where B

: is the channel bandwidth of 5MHz.

174 dBm : is the thermal noise power.

Compare the estimated noise figure to the desired noise figure of 5.4dB (Section 3.2.3.1) for a confidence of the receiver sensitivity. The measurement setup is shown in Figure 59.

Signal Generator

Receiver

Computer

analog output I or Q

RMS Voltmeter

AGC Code Generator

RMS – Root Mean Square

Figure 59.

Receiver sensitivity test setup.

The computer is used to set the channel of the radio. The test is conducted on the middle channel. The AGC code generator provides the command code to set the receiver gain.

Radio Performance

96

The signal generator provides the RF test signal. The receiver output is the I or Q analog signal from the receiver. The root-mean-square (RMS) voltmeter measures the receiver output.

Measurement Procedure:

1. Set the receiver to operate on the middle channel (i.e. 2142.5MHz). 2. Set the AGC command code for 80 (i.e. 1010000B binary) for the minimum receiver gain. 3. Set the output frequency of the signal generator for 2142.6MHz and the output level for -33dBm. Offset the frequency of the signal generator by 100KHz to produce a 100KHz tone at the I and Q analog outputs for measurement. 4. Measure the I (or Q) analog output with the RMS voltmeter. Adjust the variable resistor (Appendix C-4: R29 or R30) in the AGC board for 350mVrms (or 1Vpp) analog output. 5. Set the RF level of the signal generator for –113dBm and turn off the RF output. 6. Set the AGC command code for 0 (i.e. 0000000B binary) for the maximum receiver gain. 7. Measure the I (or Q) analog output with the RMS voltmeter. It measures the noise level in the receiver. 8. Turn on the RF output of the signal generator. 9. Increase the RF level of the signal generator until the RMS reading increases by 3dB. The 3dB increase means that the power of the receiver output is equal to the noise power. The RF output level of the signal generator is equal to the MDS of the receiver.

The measured MDS is approximately –102dBm and gives 5dB noise figure.

4.2.2

AGC Performance

The test setup in Figure 59 is applicable to this measurement.

Radio Performance

97

Measurement Procedure

1. Set the receiver to operate on the middle channel (i.e. 2142.5MHz). 2. Set the AGC command code for 80 (i.e. 1010000B) for the minimum receiver gain. 3. Set the output frequency of the signal generator for 2142.6MHz and the output level for -33dBm. Offset the frequency of the signal generator by 100KHz to produce a 100KHz tone at the I and Q analog outputs for measurement. 4. Measure the I (or Q) analog output with the RMS voltmeter. Adjust the variable resistor (Appendix C-4: R29 or R30) in the AGC board for 350mVrms (or 1Vpp) analog output. 5. Increase the AGC command code by 5. 6. Reduce the output level of the signal generator to restore the analog output level of procedure 4. 7. Record the output level of the signal generator, and the voltages of the front-end and back-end AGC drivers. 8. Repeat the procedure 5 to 7 until the I analog output is too noisy to measure. It is likely at the command code of 5 (i.e. 0000101B binary). Receiver AGC Characteristic -30

5

-40

4.5

4

-50

3.5 -60 3 -70 2.5 -80 2 -90 1.5 -100

1

-110

0.5 RF Input

-120

0 0

10

20

30

40

50

60

70

80

Front-end AGC Back-end AGC

AGC Command Code in decimal (0-80)

Figure 60.

AGC performance.

Radio Performance

98

The curves of the front-end AGC driver voltage (Front-end AGC) and the back-end AGC driver voltage (Back-end AGC) show that the performance of the AGC drivers matches the PSPICE simulation result shown in Figure 41.

The receiver RF input power curve (RF Input) shows that the back-end AGC of the receiver responds to the command code linearly but the front-end AGC behaves nonlinearly. The back-end AGC operates at the 70MHz IF frequency, while the front-end AGC operates at the 2142.5MHz RF frequency. The device linearity is better at the low frequency than at the high frequency. The analog output becomes too noisy to measure as the RF input level is less than –100dBm. However, interpolating the curve for the RF input power level at the zero AGC command code shows that the level is –113dBm and meets the design target of 80dB control range.

4.2.3

Receiver Desense

The receiver desense is measured based on the minimum detectable signal (MDS) degradation. The setup in Figure 59 is applicable to the this measurement. The MDS of the receiver, when the transmitter is turned off, is measured to be -102dBm. The transmitter is turned on and the MDS measurement is repeated. The difference of the MDS readings is the receiver desense. The measurement shows no observable receiver desense.

4.2.4

Adjacent Channel Selectivity

The adjacent channel selectivity is measured based on the MDS comparison. The setup in Figure 59 is applicable to this measurement.

Measurement Procedure

1.

Set the output frequency of the signal generator for 2147.5MHz (5MHz or 1 channel away the middle channel).

Radio Performance

99

2.

Turn on the transmitter of the radio.

3.

Set the receiver to operate on the middle channel (i.e. 2142.5MHz).

4.

Set the AGC command code for 0 (i.e. 0000000B binary) for the maximum receiver gain.

5.

Turn off the RF output of the signal generator.

6.

Measure the I (or Q) analog output with the RMS voltmeter. It measures the noise level in the receiver.

7.

Turn on the RF output of the signal generator.

8.

Increase the RF output level until the measured level of the RMS voltmeter increases by 3dB.

Compare the RF output level of the signal generator to the MDS of the receiver measured in Section 4.2.1. The difference of the readings is the adjacent channel selectivity. The measured adjacent channel selectivity is 70dB and meets the above 33dB specification. The measured 70dB adjacent channel selectivity is less than the predicted 95dB selectivity. The discrepancy is due to the board feed-through.

4.2.5

Intermodulation Selectivity

The intermodulation selectivity is measured based on the MDS comparison. Two signal generators and a power combiner are required to generate the intermodulation products. The measurement setup is shown in Figure 61. Signal Generator

I or Q Power Combiner

Signal Generator

10dB PAD

Receiver

Computer

Figure 61.

analog output

RMS Voltmeter

AGC Code Generator

Intermodulation selectivity test setup.

Radio Performance

100

Measurement Procedure 1.

Set the output frequency of one signal generator for 2152.5MHz (10MHz or 2 channels away the middle channel) and the output frequency of the second signal generator for 2162.5MHz (20MHz or 4 channels away the middle channel).

2.

Turn on the transmitter of the radio. The 10dB pad between the radio and the signal generator prevents too much transmit power from getting into the signal generator.

3.

Set the receiver to operate on the middle channel (i.e. 2142.5MHz).

4.

Set the AGC command code for 0 (i.e. 0000000B binary) for the maximum receiver gain.

5.

Turn off the RF output of the signal generator.

6.

Measure the I (or Q) analog output with the RMS voltmeter. It measures the noise level in the receiver.

7.

Turn on the RF output of the signal generator.

8.

Increase the RF output levels of the two signal generators and keep the generators at the same output levels. Increase the generator level until the measured level of the RMS voltmeter increases by 3dB.

Compare the RF output levels of the generators to the MDS of the receiver measured in Section 4.2.1. The difference of the readings is the intermodulation selectivity. The measured intermodulation selectivity is 62dB and meets the above 60dB specification.

Radio Performance

101

4.2.6

AFC Characteristic

This measures the frequency error of the AFC output verse the AFC command code (1127). The nominal frequency of the AFC is 140MHz. The AFC provides a ±2.2ppm control range as shown in Figure 62. This is close to the ±2ppm specification. Automatic Frequency Control (AFC) Characteristic 2.5

2

1.5

1

0.5

0 0

20

40

60

80

100

120

140

-0.5

-1

-1.5

-2

-2.5 AFC Command Code in decimal (0-127)

Figure 62.

The AFC characteristic.

Radio Performance

102

5. Conclusions 5.1

Summary

A radio that complies with the radio specifications of the W-CDMA system was built. The design methodology and hardware implementation of the radio has been presented. The radio meets all the specifications except the adjacent channel power. The linear QPSK modulation and the zero guard band of the W-CDMA system imposed a stringent adjacent channel power specification on the transmitter design. The use of the singlestage power amplifier failed to meet this stringent specification. An peak-to-average factor simulation was performed. Based on the simulated peak-to-average factor, the analysis suggested a two-stage power amplifier design.

The traditional receiver design technique was found applicable to this radio. The WCDMA test signals are not available in the laboratory. Therefore, the direct sensitivity measurement could not be conducted. However, using MDS to estimate the receiver performance provided a level of confidence that the receiver would perform well in the field. The TPC did not behave linearly. However, the objective of the 70dB power control range was achieved. The two stage AGC design successfully maintained the noise figure and the intermodulation sensitivity of the receiver. The smooth and linear transition between the back-end and the front-end AGCs was obtained and the 80dB control range was achieved. The use of a diode for voltage limiting performed well. The AFC provided the required ±2ppm tuning range.

The approach of this radio design is to study the system requirements up front and then to translate the system requirements into circuit level requirements. This design process was successful. Only two iterations of the hardware implementation were needed before meeting all the specifications except for the adjacent channel power. The sophisticated and expensive W-CDMA test equipment was not available. Therefore, some indirect

Conclusions

103

performance measurement techniques were introduced. These techniques successfully indicated the radio performance.

5.2

Recommendations

The problem of insufficient adjacent channel power suppression needs to be addressed. The proposed two-stage power amplifier approach needs to be verified.

The power amplifier is class A for high linearity and remains the bias condition regardless the output power level. The drawback of this scheme is inefficient. For mobile terminals, power amplifier efficiency is important for the battery life.

However, power amplifiers optimized for efficiency at maximum output power do not effectively increase battery life in W-CDMA systems. Due to the power control, the average output power is much less than the maximum power [24]. A suggestion for future research is the design of power amplifiers that can maximized the amplifier efficiency over the entire transmit power range. For the W-CDMA radio, the transmit power range is from –40dBm to 30dBm.

Conclusions

104

Appendix A: Radio Specifications Mobile Receiver Parameter

Requirement

Spreading Method

Direct Sequence

Radio Access Interface

CDMA FDD

Frequency Range

2112.5 – 2167.5 MHz

Modulation (Down Link)

Data

Comments

QPSK

Spreading QPSK AFC Function

0.015 ppm per step

Receiver Sensitivity

-113 dBm (conductive)

Static BER = 10-3

Diversity

Two Rx Antennas

Switch Diversity

Spurious Response

60dB or more at 10MHz from Fo 33dB or more at 5MHz from Fo 60dB or more

CW test signal at Psens +3dB CW test signal

Adjacent Channel Selectivity Receiver Intermodulation Sensitivity AGC

>80dB Dynamic Range

Traffic Channel Eb/No

6dB or less

Control Channel Eb/No

6dB or less

High Data Rate Eb/No

6dB or less

Input Impedance

Nominally 50Ω

Radio Specifications

Psens +3dB at 10 and 20MHz from Fo Under selective fading without power control Average BER = 10-3 Under selective fading without power control Average Frame Error Rate = 2x10-2 Under selective fading without power control, 200ms or less delay, Average BER = 10-6

105

Mobile Transmitter Parameter

Requirement

Radio Interface

Direct Sequence CDMA FDD 1922.5 – 1977.5 MHz

Frequency Range Modulation (Up Link) Modulation Bandwidth Limit Maximum Average Transmit Power and Information Bit Rate Frequency Stability

Data QPSK Spreading QPSK Root-Nyquist Roll-off (R=0.22) Type II 1.6W 128 kbps Within ± 1.0 ppm Within ± 1.0 ppm

Comments

99% within 4.096MHz Control Range: +20%, -50% Absolute accuracy Relative to base station pilot, using AFC at receiver

Transmission ON/OFF Ratio Power Control Range

With voice activity 25 dB With carrier on/off 70 dB 70 dB

Power Control Step Size

+ or –1 dB

Toggled by digital signal

Modulation Accuracy

12.5% or less

Error Vector Magnitude

Adjacent Channel Leakage

-40dBc in 5MHz band -60dBc in 5MHz band Transmitter Intermodulation -60dBc or less

5 MHz from Fo 10MHz from Fo External CW interferer

Spurious Emissions

-60dBc or less

All spurs

Output Impedance

Nominally 50Ω

Radio Specifications

106

Appendix B: Block Diagram RF2422 DAC

LPF

+45°

ATT

-45°

DAC

ATT ERA-1

BPF 1.9G

PA1

LPF PA2

DAC

D U P L E X E R

Transmitter

PC

Synthesizer SPLITTER

1.9G

Main Receiver

VCO To diversity receiver

260M VCO

LNA BPF TUF-3SM

ERA-5

BPF

190M

ERA-5

SCM-2500

ATT

2.1G

BPF ERA-4

ADC

70M

ERA-4

LPF

+45° DAC

AFC

÷2

140M

ADC

-45°

LPF

RF2667

DAC

AGC Not shown diversity receiver is identical.

Block Diagram

107

Appendix C-1: DAC Board

R6 510 DVCC AVCC 2 7 28 15

J1 1 20 2 21 3 22 4 23 5 24 6 25 7 26 8 27 9 28 10 29 11 30 12 31 13 32 14 33 15 34 16 35 17 36 18 37 19 DB37

1 2 3 4 5 6 7 8

CLK SLEEP

D V D D

2 4

U1 AD9708

A V D D REFLO

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

REFIO IOUTA IOUTB FSADJ D C O M

A C O M

C O M P 2

2 6

2 0

2 3

C8 .01u

C7 1u

C O M P 1 1 9

-V R7 27

16 17

R9 51

4

R4

C3

2

R8 1

22

.01u

240

21

3

1

U2A AD8072

C4 20p

3

C5 .01u

R5 510

+12V

U5 LM78L05 VI C20 1u

DVCC VO

C21 .1u -12V

U6 LM78L05 VI

AVCC 2 7 D V D D

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C18 .01u

2 4

U3 AD9708

A V D D REFLO REFIO IOUTA IOUTB FSADJ

D C O M

A C O M

C O M P 2

C O M P 1

2 6

2 0

2 3

1 9

U2B AD8072

U7 LM79L05 VI

510

1 2 3 4 5 6 7 8

G N D

.01u

DVCC

SLEEP

7

R16

C2 .01u

CLK

I

5

AVCC

15

.1u

SOSHIN LPF

C1

28

C9

510

AVCC

C6 1u

240 R2 27

R11

240 6

R3 R1 2K

R10 4

51 2

8

18

F1

R17 27

C13 16 .01u

4 2

22

240

AVCC C24 1u

VO

R19 15

U4A AD8072 1

R18

F2 1

8

2

510

C19 Q

3

AVCC

.1u

C16 1u

7 5

SOSHIN LPF

R13

R20 27

R22

240 6

18

240

R21 4

3

C14 20p

R12 2K

C25 .1u

C23 .1u

51 21

-V VO

-V

C17 1u

R14 17

C22 1u

G N D

G N D

U4B AD8072

C15 .01u

R15 510

AVCC C11 C12 .01u

Schematics

.01u

108

Appendix C-2: Modulator Board

+5V

+6V

R3 10 +5V

R2 18

C7 100p

100p

R7 10K

16 15 1 2 6

LO

C17 .01u

C11 1uF C12 1uF

C16 .01u

ISIG QSIG

RFOUT VCC2

IREF QREF

7

VCC1

LO PD GGGGGGG NNNNNNN DDDDDDD

9 11

3

0

C3 100p

U4 RF2422

I

Q

C14 .01u

C13 1u

R15 10K

R13 * C90 .01u

R16 *

R12 10

VCC

U7 U3

8 6 2 1

C2 7 100p

100p

5

C40 .01u

4 C1

R11 R6 10K

C4

L1 39n

U2 4 AT-108

C70 .01u

R4 10K

R1 10

C21 470p

R14 2.2K

R5 10K

+5V

C20 .01u

C5

to PA 100p

5

ERA-5

8 6 2 1

C6 100p

R70

3

U1 AT-108

18 R71 300

R72 300

C8 100p

7 C9 100p

8

1 1 1 1 3 4 5 0 2 3 4

R13

VCC

R9 10

R8 10 R90 VC 10

C10 100p

10

C60 470p

U5 LM78L05 VI VO G N D

C100 .01u

+5V

+12V

C15 10u

Schematics

U6 LM78L06 VI VO G N D

+6V

109

Appendix C-3: Receiver Board

+5V

+7V U20 LM78L05

Id=50uA Vd=5V

VO C13 .01u

Ant

L10 39n

C14 47p

C24 .01u

U2 AT-108

R10 10 U10

CN1

C201 .1u

4 U30

C10

L11

C21

C22 3

U1 1.8n

47p

2140M

G N D

C202 1u

C25 47p

Id=13mA meas Vd=5V

VI

7

Front End Out

47p

MGA86576

47p 5 On-board for the Soshin BPF

Off-board Duplexer

1 2 6 8

^ -10.49dBm

Off-board for Dr. Sweeney’s BPF

^ -33dBm

C23 47p

R20 100

^ -15.24dBm

^ -13.3dBm

Vgc2

CN8 1 2 HEADER 2

External Connections:

Signals x2 -

Vgc2 GND

+7V

R42 16

R41

R60

16

16

L31

L41 1u

C40 470p

L32

C63 470p

C43 470p

Vd=4.9V Id=65mA U3 SCM2500

Vd=4.9V Id=65mA

C52 U6

39n

12p

L30 39n

C30 18p

ERA-5SM

470p ERA-5SM

L51 27n

^ -23.61dBm

70M

3p 190M

C31 18p

U7 TUF-3SM C61

U4 39n ^ -15.24dBm

L60 1u

U5 C51

190M IF

C60 470p

R61 16

C44 .01u

L52 68n

^ -3.2dBm

R70 50

^ -3.95dBm

^ -22.9dBm CN5 L70 150n

C70

2nd LO

33p

CN4 R30 50

1st LO

+7V +7V

C84 .01u

R82

R83

R102

R103

12

12

12

12

C104 .01u

Vd=5V Id=78mA meas

C85 .01u

C105 .01u

L82 1.8u

L102 1.8u

Vd=5V Id=78mA meas

U9 L71

L72

C80

120n

120n

.01u

70M

C81

L90

.01u

180n

L91

C100

C71 47p

150n 70M

ERA-4SM

^ -10.3dBm

C101

CN6

U10

U8 .01u ^ -4.8dBm

^ 3.67dBm

RF2667 ERA-4SM

.01u

^ 8.77dBm

Off-board Parts External Connections: +12V

U21 LM317

CN20 1 2

VI

Is=410mA Pd=2W G N D

+7V SMA Coax x3 -

VO

To RF2667 1st LO IN 2nd LO IN

R211 R C211 .1u

C212 1000p

C214 .01u R212 R

Power x2 -

+12Vdc x1 Power GND x1

C213 10u

Schematics

110

Appendix C-4: VGC Driver Board

R1,22 CN31

680K

2 1

R2,19 110K

4

HEADER 2

U2,4A

2

1

Vgc3,4 AT-108

3 LM6132 R3,12 8

10K

R4,23 3.9K C2,4 .1u

R5,13

6 7 5

0 R7,21

R10,11

U2,4B

10K 6

6

7

R9,17

7

Vgc1,2 RF2667

R8,16 15K

10K

9.1K 12K U5A,B

U7A,B LM6132

R6,20

R25,26

5 5

CN32

R27,28 10K

LM6132

1 2

D1,2 1N4148

10K

LM6132

R29,30

HEADER 2

5K

+5V

J5

R14,24 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1

U3,P6 U3,P7 U3,P5 U3,P8 U3,P4 NC U3,P3 GND U3,P2 GND U3,P1 GND +12Vdc GND U1,P8 GND U1,P7 GND U1,P6 GND U1,P5 U1,P1 U1,P4 U1,P2 U1,P3

CONNECTOR DB25

12 U1,3 U1-J5,P15;U3-J5,P8 U1-J5,P14;U3-J5,P9 U1-J5,P1;U3-J5,P10 U1-J5,P2;U3-J5,P11 U1-J5,P3;U3-J5,P12 U1-J5,p4;U3-J5,P13 U1-J5,P5;U3-J5,P25 U1-J5,P6;U3-J5,P24

1 2 3 4 5 6 7 8

B8 B7 B6 B5 B4 B3 B2 B1 AD557

+5V

16 15 14 13 12 11 10 9

+5V R15,18 0 C3,6 no part

U6 LM78L05 VO

C61 .01u

VO VO_A VO_B GND GND VCC /CS /CE

C6 1u

G N D

VI

+12Vdc

C7 .1u

added part

Non-used parts because they are difficult to place on the layout.

Schematics

111

Appendix C-5: AFC Board

R2

R5 20K

100K 6

R8 100K

R9 7 U2B LM6132

5

U1 1 2 3 4 5 6 7 8

J2 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1

B8 B7 B6 B5 B4 B3 B2 B1

VO VO_A VO_B GND GND VCC /CS /CE

16 15 14 13 12 11 10 9

V C C

VC

C7 VO

4 R18 5K

2 .01u

G

4

+10V

B8 B7 B6 B5 B4 B3 B2 B1

3

U2A LM6132 R4 30K

U5

5V

1 2

C1 .1u

+5VD

-12V

1

3 R7

C17 1U

+5VA

C15 .1u

8

30K

AD557

1 2 3 4 5 6 7 8

R6 20K

R1 30K +5VD

4.7K

+5VD

U12

1 3

10M VCTCXO

U3F

R15

8 VO VO_A VO_B GND GND VCC /CS /CE

16 15 14 13 12 11 10 9

3

1 2

1 0

1 2

U10A LM6132

+5VD

2.4K

Synthesizer

4

U10B LM6132 7

6 +10V

R17

Vc Tx Power Control

U6 LM78L05 VI

G N D

30K

C13 .1u

+5VD

+5VA U3 P14

R19 5K

VO

C8 .1u R16 2K

+12V U13 LM78L05 VI

G N D

U3 P7

+5VA U3C

VO

+10V R13

6

150 L1 2.2u

U9

C12 .01u

4 U8 140M

Rx1 U7 LM78L10 VI G N D

C10

C9

R12

.01u

.01u

.01u

51

2 CN2

U3D 3

8

9 74HC04

U3A

C11 +10V VO

5 U3B

CN1

Schematics

U3E

8.2K

R14

5

AD557

DB25 F

C14 1u

1 1

1

Rx2 LRPS-2-1

U4 ERA-1SM

Toyo 272MT-1008A

112

Appendix C-6: Splitter Board

+7V R353 stacking assembly 180

R300

R354 180

C352 47p

CN31

24

~38mA R301 220

R302 220

-1.5dBm R314

120

L350 56nH

stacking assembly U30

+7V R313 4dB PAD

~55mA

~4.8V CN30

R350

C350

C351

*

1950M 240

47p R352 62

R351 62

C312 .01u

47p U35 ERA-3SM

C310

R310

LRPS-2-25

120 C311 47p

CN32

U31 ERA-1SM

R312 220

U32

C320

~3.7V

47p

24 R311 220

L310 56nH

20dB PAD

7dBm

47p

CN33 7dBm

LRPS-2-25 4dB PAD

R334

120 stacking assembly

Supplier - the 7V off-board LM317 Regulator +7V R333 ~55mA 120 C333 .01u CN34

R330

C331

36

470p

L330 1uH

C332 470p

U34 CN35

~3.7V

C340

U33 ERA-1SM

470p

10dBm

120M R331 150

R332 150

CN36 LRPS-2-1

10dBm

6dB PAD

* Non-used decoupling parts because power traces are short on the layout.

Schematics

113

Appendix D-1: Spurious Analysis Part 1 – Middle Channel

Input Spurious, Select LO, Tune Input, Input Filter System Input/Output Parameters Output Frequency = Difference Input Start Frequency Input Stop Frequency LO Frequency Selected Maximum Spur Table Level

997.5 3002.5 1952.5 65

MHz MHz MHz dB

Input Butterworth BPF with Fixed Bandwidth Number of Sections Filter Center Frequency Filter Bandwidth Frequency Filter Corner Attenuation Filter Maximum Attenuation

7 2142.5 60 0.1 110

MHz MHz dB dB

Spurious Data Input Freq.

Output Freq.

MHz 2142.5 2142.5 2142.5 2142.5 2142.5 2142.5 2142.5 2142.5 2142.5 2142.5

Output Spur Level (dB)

Mixer Spur

MHz

Input Spur Freq. MHz

190. 190. 190. 190. 190. 190. 190. 190. 190. 190.

1071.25 1762.5 1857.5 1889.167 2015.833 2047.5 2142.5 2540. 2666.67 2833.75

263. 110. 269. 377. 266.4 159.3 0 394. 394. 261.

Spurious Analysis

Mixer Spur

MxSPUR NxLO

Mixer Table Atten. (dB)

Input Filter Atten. (dB)

2 -1 -2 -3 3 2 1 -3 3 -2

43 0 49 47 47 49 0 64 64 41

110. 110. 110. 110. 73.1 55.2 0 110. 110. 110.

-1 1 2 3 -3 -2 -1 4 -4 3

114

Appendix D-2: Spurious Analysis Part 2 – Middle Channel

Input Spurious, Select LO, Tune Input, Input Filter System Input/Output Parameters Output Frequency = Difference Input Start Frequency Input Stop Frequency LO Frequency Selected Maximum Spur Table Level

997.5 3002.5 1952.5 65

MHz MHz MHz dB

Input Butterworth BPF with Fixed Bandwidth Number of Sections Filter Center Frequency Filter Bandwidth Frequency Filter Corner Attenuation Filter Maximum Attenuation

7 2142.5 60 0.1 110

MHz MHz dB dB

Spurious Data Input Freq.

Output Freq.

MHz 1622.5 1622.5 1622.5 1622.5 1622.5 1622.5 1622.5 1622.5 1622.5 1622.5

Output Spur Level (dB)

Mixer Spur

MHz

Input Spur Freq. MHz

330. 330. 330. 330. 330. 330. 330. 330. 330. 330.

1141.25 1622.5 1787.5 1842.5 2062.5 2117.5 2282.5 2493.333 2713.333 2763.75

263. 110. 269. 377. 180.4 49. 75.4 394. 394. 261.

Spurious Analysis

Mixer Spur

MxSPUR NxLO

Mixer Table Atten. (dB)

Input Filter Atten. (dB)

2 -1 -2 -3 3 2 1 -3 3 -2

43 0 49 47 47 49 0 64 64 41

110. 110. 110. 110. 44.5 . 75.4 110. 110. 110.

-1 1 2 3 -3 -2 -1 4 -4 3

115

Appendix D-3: Spurious Analysis Part 3 - Middle Channel Input Spurious, Select LO, Tune Input, Input Filter System Input/Output Parameters Output Frequency = Difference Input Start Frequency Input Stop Frequency LO Frequency Selected Maximum Spur Table Level

100 400 260 65

MHz MHz MHz dB

Input Butterworth BPF with Fixed Bandwidth Number of Sections Filter Center Frequency Filter Bandwidth Frequency Filter Corner Attenuation Filter Maximum Attenuation

7 190 4.6 1 40

MHz MHz dB dB

Spurious Data Output Freq.

MHz 190 190 190 190 190 190 190 190 190 190 190 190 190 190 190 190 190 190

Input Freq.

Output Spur Level (dB)

Mixer Spur

MHz

Input Spur Freq. MHz

70. 70. 70. 70. 70. 70. 70. 70. 70. 70. 70. 70. 70. 70. 70. 70. 70. 70.

110. 150. 165. 177.5 190. 196.667 212.5 236.667 246. 274. 283.333 298. 307.5 323.333 326. 330. 342.5 350.

166. 169. 134. 221. 0 169. 221. 169. 259. 259. 169. 264. 224. 174. 264. 40. 224. 255.

Spurious Analysis

Mixer Spur

MxSPUR NxLO

Mixer Table Atten. (dB)

Input Filter Atten. (dB)

3 -3 2 -4 -1 3 4 -3 -5 5 3 -5 -4 -3 5 1 4 -5

46 49 54 61 0 49 61 49 59 59 49 64 64 54 64 0 64 55

40. 40. 40. 40. 0 40. 40. 40. 40. 40. 40. 40. 40. 40. 40. 40. 40. 40.

-1 2 -1 3 1 -2 -3 3 5 -5 -3 6 5 4 -6 -1 -5 7

116

Appendix D-4: Spurious Analysis Part 1 - Bottom Channel

Input Spurious, Select LO, Tune Input, Input Filter System Input/Output Parameters Output Frequency = Difference Input Start Frequency Input Stop Frequency LO Frequency Selected Maximum Spur Table Level

997.5 3002.5 1922.5 65

MHz MHz MHz dB

Input Butterworth BPF with Fixed Bandwidth Number of Sections Filter Center Frequency Filter Bandwidth Frequency Filter Corner Attenuation Filter Maximum Attenuation

7 2142.5 60 0.1 110

MHz MHz dB dB

Spurious Data Input Freq.

Output Freq.

MHz 2112.5 2112.5 2112.5 2112.5 2112.5 2112.5 2112.5 2112.5 2112.5 2112.5 2112.5

Output Spur Level (dB)

Mixer Spur

MHz

Input Spur Freq. MHz

190. 190. 190. 190. 190. 190. 190. 190. 190. 190. 190.

1056.25 1732.5 1827.5 1859.167 1985.833 2017.5 2112.5 2500. 2626.667 2788.75 2978.75

263. 110. 269. 377. 306.6 193.6 .1 394. 394. 261. 261.

Spurious Analysis

Mixer Spur

MxSPUR NxLO

Mixer Table Atten. (dB)

Input Filter Atten. (dB)

2 -1 -2 -3 3 2 1 -3 3 -2 2

43 0 49 47 47 49 0 64 64 41 41

110. 110. 110. 110. 86.5 72.3 .1 110. 110. 110. 110.

-1 1 2 3 -3 -2 -1 4 -4 3 3

117

Appendix D-5: Spurious Analysis Part 2 – Bottom Channel

Input Spurious, Select LO, Tune Input, Input Filter System Input/Output Parameters Output Frequency = Difference Input Start Frequency Input Stop Frequency LO Frequency Selected Maximum Spur Table Level

997.5 3002.5 1922.5 65

MHz MHz MHz dB

Input Butterworth BPF with Fixed Bandwidth Number of Sections Filter Center Frequency Filter Bandwidth Frequency Filter Corner Attenuation Filter Maximum Attenuation

7 2142.5 60 0.1 110

MHz MHz dB dB

Spurious Data Input Freq.

Output Freq.

MHz 1592.5 1592.5 1592.5 1592.5 1592.5 1592.5 1592.5 1592.5 1592.5 1592.5

Output Spur Level (dB)

Mixer Spur

MHz

Input Spur Freq. MHz

330. 330. 330. 330. 330. 330. 330. 330. 330. 330.

1126.25 1592.5 1757.5 1812.5 2032.5 2087.5 2252.5 2453.333 2673.333 2718.75

263. 110. 269. 377. 239.9 91.7 61.2 394. 394. 261.

Spurious Analysis

Mixer Spur

MxSPUR NxLO

Mixer Table Atten. (dB)

Input Filter Atten. (dB)

2 -1 -2 -3 3 2 1 -3 3 -2

43 0 49 47 47 49 0 64 64 41

110. 110. 110. 110. 64.3 21.4 61.2 110. 110. 110.

-1 1 2 3 -3 -2 -1 4 -4 3

118

Appendix D-6: Spurious Analysis Part 1 – Top Channel

Input Spurious, Select LO, Tune Input, Input Filter System Input/Output Parameters Output Frequency = Difference Input Start Frequency Input Stop Frequency LO Frequency Selected Maximum Spur Table Level

997.5 3002.5 1977.5 65

MHz MHz MHz dB

Input Butterworth BPF with Fixed Bandwidth Number of Sections Filter Center Frequency Filter Bandwidth Frequency Filter Corner Attenuation Filter Maximum Attenuation

7 2142.5 60 0.1 110

MHz MHz dB dB

Spurious Data Input Freq.

Output Freq.

MHz 2167.5 2167.5 2167.5 2167.5 2167.5 2167.5 2167.5 2167.5 2167.5 2167.5

Output Spur Level (dB)

Mixer Spur

MHz

Input Spur Freq. MHz

190. 190. 190. 190. 190. 190. 190. 190. 190. 190.

1083.75 1787.5 1882.5 1914.167 2040.833 2072.5 2167.5 2573.333 2700. 2871.25

263. 110. 269. 377. 225.1 121.4 . 394. 394. 261.

Spurious Analysis

Mixer Spur

MxSPUR NxLO

Mixer Table Atten. (dB)

Input Filter Atten. (dB)

2 -1 -2 -3 3 2 1 -3 3 -2

43 0 49 47 47 49 0 64 64 41

110. 110. 110. 110. 59.4 36.2 . 110. 110. 110.

-1 1 2 3 -3 -2 -1 4 -4 3

119

Appendix D-7: Spurious Analysis Part 2 – Top Channel

Input Spurious, Select LO, Tune Input, Input Filter System Input/Output Parameters Output Frequency = Difference Input Start Frequency Input Stop Frequency LO Frequency Selected Maximum Spur Table Level

997.5 3002.5 1977.5 65

MHz MHz MHz dB

Input Butterworth BPF with Fixed Bandwidth Number of Sections Filter Center Frequency Filter Bandwidth Frequency Filter Corner Attenuation Filter Maximum Attenuation

7 2142.5 60 0.1 110

MHz MHz dB dB

Spurious Data Input Freq.

Output Freq.

MHz 2307.5 2307.5 2307.5 2307.5 2307.5 2307.5 2307.5 2307.5 2307.5 2307.5

Output Spur Level (dB)

Mixer Spur

MHz

Input Spur Freq. MHz

330. 330. 330. 330. 330. 330. 330. 330. 330. 330.

1153.75 1647.5 1812.5 1867.5 2087.5 2142.5 2307.5 2526.667 2746.667 2801.25

263. 110. 269. 377. 111.1 49. 85.1 394. 394. 261.

Spurious Analysis

Mixer Spur

MxSPUR NxLO

Mixer Table Atten. (dB)

Input Filter Atten. (dB)

2 -1 -2 -3 3 2 1 -3 3 -2

43 0 49 47 47 49 0 64 64 41

110. 110. 110. 110. 21.4 0 85.1 110. 110. 110.

-1 1 2 3 -3 -2 -1 4 -4 3

120

Appendix E: PLL Programming Information The Harris PLL chip provides the following possible divider values. Dual Modulus Prescaler P:

32/33 or 64/65 (RF)

8/9 or 16/17 (IF)

7-Bit Swallow Divider A:

0 ~ 127 (RF)

0 ~ 15 (IF)

11-Bit Program Divider B:

3 ~ 2047

RF Synthesizer To operate the RF synthesizer for the transmitting band (1922.5-1977.5MHz), the change of the divider values is on the swallow divider. All the other dividers are kept no change. Table E-1 lists all the divider values to the channels.

Table E-1.

Divider values to the RF synthesizer. Note that the least significant bit is on left rather than on right as usual.

Dividers Decimal

R 4

A *

N B 24

P 32

LSB Control

R Divider Prog Mode MSB C1 C2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 RF R dvdr 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 Control

A Divider C1 C2 1 2 3 4 RF N dvdr 1 1 1 0 0 0 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0

PLL Programming Information

Prog Mode

N Divider 5 0 0 0 0 0 0 0 0 1 1 1 1

6 0 0 0 0 0 0 0 0 0 0 0 0

7 0 0 0 0 0 0 0 0 0 0 0 0

B Divider 8 9 10 11 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1

12 1 1 1 1 1 1 1 1 1 1 1 1

13 0 0 0 0 0 0 0 0 0 0 0 0

14 0 0 0 0 0 0 0 0 0 0 0 0

15 0 0 0 0 0 0 0 0 0 0 0 0

16 0 0 0 0 0 0 0 0 0 0 0 0

17 0 0 0 0 0 0 0 0 0 0 0 0

18 0 0 0 0 0 0 0 0 0 0 0 0

19 0 0 0 0 0 0 0 0 0 0 0 0

20 0 0 0 0 0 0 0 0 0 0 0 0

* A 1 3 5 7 9 11 13 15 17 19 21 23

121

(MHz) 1922.5 1927.5 1932.5 1937.5 1942.5 1947.5 1952.5 1957.5 1962.5 1967.5 1972.5 1977.5

RF R-Divider

The first two bits identify which dividers to be programmed. Here they are ‘01’ for the RF R-divider. Then the bits 1 to 15 form the divider value that always is 4 to the radio. The final five bits are the program modes and they are:

Description

‘0’

‘1’

Set

RF Phase Detector Polarity

-ve

+ve

1

17

RF ICPO – Charge Pump Current

low

high

0

18

RF Detector O/P State

normal

high Z

0

19

RF Lock Detect

no

yes

1

20

RF FO Out

no

yes

0

Bit 16

RF N-Divider

Again, the first two bits identify the selected divider and they are ‘11’. The bits 1 to 7 are the A-swallow divider value. Its value is changed based on the wanted frequency and the used values are listed in Table E-1. Then the bits 8 to 18 form the B-divider value and it always is 24. The last two bits select the prescaler P-counter value (32 or 64) and power mode (up or down). Set the bit 19 to ‘0’ for P-counter=32 and the bit 20 to ‘0’ for power up.

PLL Programming Information

122

260MHz IF Synthesizer

This is a fix frequency synthesis. All of divider values are fixed for the wanted frequency of 260MHz. The IF synthesizer needs to program once as long as it is powered on. Table E-2 lists the divider values.

Table E-2.

Dividers decimal

Divider values to the IF synthesizer. The least significant bit is on left.

R 4

A 0

N B 13

P 8

LSB Control

IF R dvdr

R Divider Prog Mode MSB C1 C2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 Control

IF N dvdr

Prog Mode

N Divider

A Divider B Divider C1 C2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0

IF R-Counter

The first two bits identify which dividers to be programmed. Here they are ‘00’ for the IF R-counter. Then the bits 1 to 15 form the divider value that always is 4 to the radio. The final five bits are the program modes and they are:

Description

‘0’

‘1’

Set

IF Phase Detector Polarity

-ve

+ve

1

17

IF ICPO – Charge Pump Current

low

high

0

18

IF Detector O/P State

normal

high Z

0

19

IF Lock Detect

no

yes

1

20

IF FO Out

no

yes

0

Bit 16

PLL Programming Information

123

IF N-Counter

Similarly, the first two bits identify the divider to be selected. In this case, they are ‘10’. The bits 1 to 7 are the A-swallow divider value. It always is 0 for 260MHz. Then the bits 8 to 18 form the B-counter value and it always is 13. The last two bits select the prescaler P-divider value (8 or 16) and power mode (up or down). Set the bit 19 to ‘0’ for Pcounter=8 and the bit 20 to ‘0’ for power up.

Remark:

-

The divider values are stored individually. Changing the value of one divider does not affect the values of the other dividers.

-

In practice, program the R-counter and then the N-counter in a program cycle.

-

The divider values will stay as long as Vcc is supplied. However, refreshing them in every program cycle is valid.

-

Send the data to the synthesizer with the MSB at first and a timing diagram is shown Figure E-1.

#20 Data

#19

#10

#9

MSB

#1

Control bit:LSB LSB

Clock

LE or LE

Figure E-1.

Timing diagram of loading divider values

PLL Programming Information

124

References [1]

Michael H. Callendar, “International Mobile Telecommunications – 2000 Standard Efforts of the ITU,” IEEE Personal Communications, vol. 4, no. 4, pp. 6-7, August 1997.

[2]

Akio Sasaki, Masami Yabusaki and Syuichi Inada, “The Current Situation of IMT-2000 Standardization Activities in Japan,” IEEE Communications Magazine, vol. 36, no. 9, pp. 145-153, September 1998.

[3]

Fumiyuki Adachi, Mamoru Sawahashi and Hirohito Suda, “Wideband DS-CDMA for Next Generation Mobile Communications Systems,” IEEE Communications Magazine, vol. 36, no. 9, pp. 56-69, September 1998.

[4]

Stephen McClelland and Bhawani Shankar, “Mobilizing the Third Generation,” Telecommunications (Americas Edition), vol. 31, no. 11, pp. 50-52,54, November 1997.

[5]

Fabio Leite, Richard Engelman, Shunsuke Kodama, Horst Mennenga and Sabah Towaij, “Regulatory Considerations Relating to IMT-2000,” IEEE Personal Communications, vol. 4, no. 4, pp. 14-19, August 1997.

[6]

Atsushi Fukasawa, Takuro Sato, Yumi Takizawa, Toshio Kato, Manabu Kawabe and Reed E. Fisher, “Wideband CDMA System for Personal Radio Communications,” IEEE Communications Magazine, vol. 34, no. 10, pp. 116123, October 1996.

[7]

Erik Dahlman, Bjorn Gudmundson, Mats Nilsson and Johan Skold, “UMTS/IMT2000 Based on Wideband CDMA,” IEEE Communications Magazine, vol. 36, no. 9, pp. 70-80, September 1998.

[8]

Fumiyuki Adachi and Mamoru Sawahashi, “Wideband Multi-rate DS-CDMA Mobile Radio Access,” 1997 Asia Pacific Microwave Conference Proceedings, vol. 1 of 3, pp. 149-152, December 2-5, 1997.

[9]

Esmael H. Dinan and Bijan Jabbari, “Spreading Codes for Direct Sequence CDMA and Wideband CDMA Cellular Networks,” IEEE Communications Magazine, vol. 36, no. 9, pp. 48-54, September 1998.

[10]

Japan’s Revised Proposal for Candidate Radio Transmission Technology on IMT2000: W-CDMA, Revised Proposal (ver. 1.1), Association of Radio Industries and Business (ARIB) IMT-2000 Study Committee, September 1998.

[11]

Raymond A. Birgenheier, “Overview of Code-Domain Power, Timing, and Phase Measurements,” Hewlett-Packard Journal, vol. 47, no. 1, pp. 73-93, February 1996.

References

125

[12]

Theodore S. Rappaport, Wireless Communications Principles and Practice, Prentice-Hall PTR, New Jersey, 1996.

[13]

Victor Fung, “Bit Error Simulation of FSK, BPSK, and π/4 DQPSK in Flat and Frequency-Selective Fading Mobile Radio Channels using Two-Ray and Measurement-Based Impulse Response Models”, Master Thesis in Electrical Engineering, Virginia Tech., August 1991.

[14]

John G. Proakis, Digital Communications, WCB/McGraw-Hill, 1995.

[15]

Biasing ERA Amplifiers, Mini-Circuits Application Note AN-60-010, September 18, 1998.

[16]

The ARRL Handbook for Radio Amateurs, 26th Edition, American Radio Relay League, Connecticut, 1992.

[17]

Bernard Sklar, Digital Communications Fundamentals and Applications, Prentice-Hall PTR, New Jersey, 1988.

[18]

Behzad Razavi, RF Microelectronics, Prentice-Hall PTR, New Jersey, 1998.

[19]

Robert R. Kyle, Spurious and Filter Analysis, Artech House Inc., 1996.

[20]

William E. Sabin and Edgar O. Schoenike, editors, Single-Sideband Systems and Circuits, McGraw-Hill, 1987.

[21]

Charles W. Bostian, “EE4606 Radio Engineering Lecture Notes”, Spring 1998.

[22]

Tim Bozych, “Using the HFA3524 Evaluation Board,” Harris Application Note AN9630, November 1996.

[23]

William F. Egan, Phase Lock Basics, Wiley, 1998.

[24]

John F. Sevic, "Statistical Characterization of RF Power Amplifier Efficiency for CDMA Wireless Communication Systems," Proceedings of 1997 Wireless Communications Conference, pp. 110-113, August 1997.

References

126

Vita

Cheung, Tze Chiu was born in Hong Kong, on July 3, 1966. He received his Higher Diploma in Electronic Engineering from the Hong Kong Polytechnic in June 1987. After his graduation, he worked as a Product Engineer in Video Technology Engineering Limited. In January 1989, he was transferred to Technophone Manufacturing Limited, a joint-venture

company

between

Video

Technology

Engineering

Limited

and

Technophone, as a Senior Test Engineer. In 1992, he joined Wong’s Electronics Company, Limited as a Senior RF Engineer, where he worked on the design and development of cordless and analog cellular phones.

In March 1995, he moved to America and resided in Brooklyn, New York. He pursued his undergraduate degree in Polytechnic University and received his Bachelor of Science degree in Electrical Engineering in June 1997. From 1996 to 1997, he worked in Newtronix Communications, Inc. as a part-time engineer. He came to Virginia Tech in the fall of 1997 for his master study in Electrical Engineering. In January 1998, he joined the Center for Wireless Telecommunications at Virginia Tech, where he worked on the 2GHz W-CDMA radio transceiver as his master thesis topic.

Vita

127