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CHARACTERIZATION OF BULK MICROMACHINED TUNNELING TIP INTEGRATED WITH POSITIONING ACTUATOR M. Mita∗ , H. Toshiyoshi∗ , K. Kakushima∗ , G. Hashiguchi∗∗ , D. Kobayashi† , J. Endo‡ , Y. Wada‡ , and H. Fujita∗ ∗

IIS., University of Tokyo,

∗∗

Kagawa University, † Tokyo Denki University, ‡ Hitachi LTD.

ABSTRACT We have successfully fabricated a tunneling tip integrated with a silicon micromachined electrostatic actuator of high aspect ratio. Tip sharpness has been investigated by scanning over carbon graphite as an atom scale.

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INTRODUCTION

We have been developing an integrated tunneling spectroscope by using silicon micromachining processes [1]. The main goal of our project is to visualize the tunneling gap in the transmission electron microscope (TEM) to elucidate nanomechatronic physics of the tunneling phenomena at a highly concentrated electrostatic field and high current density. Our approach to create such extreme electrophysical condition is to use a very sharp tunneling tip with a small tunneling gap. We have successfully developed a tunneling tip with an electrostatic micropositioning actuator by Deep RIE (DRIE) of a silicon-oninsulator (SOI) wafer. The sharpness of the tip has been characterized by scanning over the surface of carbon graphite as a reference sample. The micro tunneling unit (Figure 1) consists of two parts: an electrostatic microactuator of high aspect ratio and a nano-wire tunneling tip. It has been known that a large pull-in attraction force acts on the tunneling tip and that the control system falls into unstable oscillation when the actuator is not as powerful as the attraction force [2]. We have overcome this pull-in instability by using high-aspect ratio structures for the supporting suspension of large spring constant and by using the comb-drive mechanism of large electrostatic force. A sharp tunneling tip is made at the same etching process of making these positioning mechanism. We also fabricated sharper tips whose geometrical shape could be defined by the anisotropic wet etching profile of single crystalline silicon.

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Figure 1: Layout of electrostatic comb-drive actuator and tunneling tip Figure 2 shows the fabrication process: (a) Aluminum masking layers are prepared on both sides of a 50-2-500µm SOI wafer. The front side aluminum has been patterned into the shape of a comb-drive with a tunneling tip and anchoring pads. The backside aluminum is for defining isolation trenches around the chip and for making a through-hole for TEM observation. (b) The front side silicon layer is patterned by DRIE to define the actuator. At the same time, a sharp tip is formed thanks to the slanted sidewalls meeting at the tip, where the lower part of silicon has been removed to leave a thin silicon bridge on the top [3, 4]. (c) A through hole and isolation grooves are formed by the second DRIE from the backside. (d) Finally, the structure is sacrificial-released by removing the buried oxide in HF. During this step, each piece of chip is released from the silicon wafer. After drying, the chips are ready to be metallized by vacuum evaporation of titanium, platinum and gold, for example. The tunneling tip fabrication process is shown in Fig. 3. The profile of Deep RIE is not completely vertical. Then the slanted sidewall make a bridge at the narrow pattern as tunnel tip. We used this process to fabricate sharp tunneling tip.

FABRICATION PROCESS 1

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3

Al Si

SiO2

Si

(a) Al patterning

(c) Deep RIE from back side

(b) Deep RIE from top side

FABRICATION RESULT

Figure 4 shows a scanning electron microscope (SEM) view of a fabricated tunneling device. The chip size is 2.5 mm × 2.5 mm in area and 0.5 mm in thickness. The suspension width is 8 µm, and its length is 800 µm. The thickness of structure is 50 µm. Figure 5 shows a close-up view of the tunneling tip on the left-hand side, which is driven by the actuator toward the counter electrode seen on the right-hand side. The radius of the tip has been measured to be 200 nm, and the length to be 8 µm.

(d) Release

Figure 2: Fabrication process

If the etching profile is perfect vertical















Real ICP-RIE etching profile











































































Figure 4: SEM view of the tunneling unit chip

Oxidation and SiO2 removal

Figure 3: Tip fabrication process

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Figure 5: Close-up SEM view of the tunneling tips

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MEASUREMENT

To evaluate the tunneling tip, we removed the counter electrode and attached the whole chip (including the tip and suspensions; the micro actuator was not energized) to a tube piezo-actuator of the conventional STM. We used this setup as a test bench for evaluating our tunneling tip by observing the surface of carbon graphite with the tip. Figure 6

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Tunnel bias

Pre-AMP

para-capacitance

STM controller

shows the carbon graphite image. Upper figure is STM image of the carbon graphite and lower is the cross-sectional view at white line in the upper figure. In this figure, the atomic resolution of the carbon (0.25 nm) has been obtained along the X-direction of the image, by which we conclude that out tip is sharp enough to visualize and localize the tunneling phenomena when we employ it for in-situ observation in the TEM. The resolution in the Y-direction has been jammed probably due to the vibration of the suspended tip.

Driving electrode Tunnel Tip

Figure 7: Diagram of tunneling gap control system

Y direction

Tunnel current:0.67nA

Driving voltage:90V

Tunnel bias:0.5V

X direction

Figure 8: Tunnel current controlling result

0.256nm

well-defined geometry of the tunneling tip to evaluate electric field and to construct a theoretical model of the phenomenon at tunnel tip. We also tried to Figure 6: STM image of carbon graphite scanned fabricate sharper tunneling tip by combined DRIE with silicon micromachined tunnel tip carbon process with anisotropic wet etching of silicon. graphite image. Fabrication process is shown in Fig. 9. (a) Silicon nitride layer is deposited on a bare silicon by LPCVD We have also demonstrated controlling the tunnel- and then patterned by patterned by CCP-RIE (Caing gap by monitoring the tunneling current between pacitive Coupled Plasma RIE). This SiN patterns are the built-in tunneling tip and the counter electrode used as a mask for LOCOS (local oxidation) proon our chip (Fig. 7). We found that the tunneling cess. (b) Comb-drive actuator is formed by DRIE. current in our previous device had a poor SN ratio (c) The whole structure is then thermally oxidized due to the parasitic capacitive leak from the comb- except the silicon under the silicon nitride mask (LOactuator, where a relative large voltage was applied. COS). (d) After nitride removal by CCP-RIE, (e) the Therefore, we improved the layout design by placing tunneling tips are formed by TMAH anisotropic wet an electrostatic shield around the tunneling gap to etching. In this step, the tip shape was determined by the crystallographic orientation of silicon. The shape suppress the noise level. The result of controlling the tunneling gap is shown and the dimension of the tip depend on the thickness in Fig. 8. We adjusted out controller to obtain typical of silicon layer [5]. In Fig. 10, two pairs of sharp tips can be seen at the tunneling current of 0.7 nA under a bias voltage of end of the electrodes. Those tips are automatically 0.5 V. In this experiment, our device controlled the made due to the nature of anisotropic wet etching of tunneling gap by monitoring the tunneling current. silicon under the mask layout we used. Mutual distance of one tip pair has been intentionally designed to be shorter than that of the other pair, so that we 5 Geometrically-defined may use the first pair as tunneling tips. tunneling tip After the formation of the tips, the surface is therThe theoretical team in our project [1] requested mally oxidized at a low temperature (950 deg C) to

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